TSMC's next real shrink isn't A16. It's A14, a 1.4nm-class node that TSMC says will be a bigger node than N2, even though N2 already had more than 20 customer tape-outs and over 70 in the pipeline by April 2026.
That's a big claim for a process that won't reach volume production until 2028. It also hides a design choice most coverage skips: A14 launches without backside power, and TSMC has pushed its Super Power Rail onto a separate A14 derivative called A12.
This full guide covers what TSMC A14 is, its speed, power and density numbers against N2, NanoFlex Pro, second-generation nanosheets, why backside power waits, the A13 and A12 family, the no High-NA decision, Fab 25 in Taichung, who is designing on it, how it compares with Intel 14A and Samsung SF1.4, and the honest limits, all as of October 29, 2026.
Last updated: October 29, 2026.
Key Takeaways
- TSMC A14 is a full-node shrink from N2 with 10% to 15% more speed or 25% to 30% less power and close to 20% more chip density, per TSMC's July 2026 earnings call.
- A14 enters risk production in 2027 and volume production in 2028, and TSMC expects it to be a bigger node than N2.
- A14 ships with front-side power. Super Power Rail arrives on the A14 platform as A12 in 2029, alongside the A13 optical shrink.
- TSMC builds A14 without High-NA EUV; Kevin Zhang said its gains are "very substantial without using High-NA".
- Honest limit: the only public A14 tape-out is Socionext's test chip, and the $45,000 wafer estimate is a report, not a TSMC price.
What TSMC A14 actually is
TSMC A14 is the foundry's 1.4nm-class logic process and its second generation of nanosheet gate-all-around (GAA) transistors. TSMC unveiled it at its North America Technology Symposium in Santa Clara on April 23, 2025, with production planned for 2028.
Here's the key distinction. A16, due before it, is essentially N2P with Super Power Rail backside power on first-generation nanosheets. A14 is an all-new node: new transistor, new standard cells, new design rules, and a full-node jump in density.
That means A14 needs new IP, new EDA flows and new design work, unlike N2P or N2U, which reuse N2 IP. Tom's Hardware notes that A14 will require new IPs, optimizations and EDA software compared with N2P and A16.
The name is marketing. "A14" means angstrom-class 14, not a 1.4 nm feature anywhere on the chip. Inside Deep Tech's GAAFET and nanosheet guide explains what angstrom names do and don't describe.
TSMC A14 specs at a glance
TSMC has published A14 gains only as ranges against N2, not absolute pitches. The table compares A14 with its neighbors on the roadmap, using TSMC's own comparison baselines.
| Node | Compared with | Speed (same power) | Power (same speed) | Density | Power delivery | Volume production |
|---|---|---|---|---|---|---|
| N2 | N3E | Baseline for A14 | Baseline for A14 | Baseline for A14 | Front side | 4Q 2025 |
| A16 | N2P | +8% to 10% | -15% to 20% | 1.07x to 1.10x | Super Power Rail | 2027 |
| N2U | N2P | +3% to 4% | -8% to 10% | 1.02x to 1.03x | Front side | 2028 |
| A14 | N2 | +10% to 15% | -25% to 30% | 1.20x chip, 1.23x logic | Front side | 2028 |
| A13 | A14 | DTCO gains | DTCO gains | About 6% smaller die | Front side | 2029 |
| A12 | A16 | Not disclosed | Not disclosed | Not disclosed | Super Power Rail, 2nd gen | 2029 |
Source: TSMC roadmap via Tom's Hardware (April 2026); A14 figures from TSMC's 2Q26 earnings call and the 2025 symposium. Chip density is TSMC's mixed design of 50% logic, 30% SRAM and 20% analog.
Two things stand out. First, TSMC presented the A14 numbers again in 2026 without any changes, which suggests development hasn't forced a downgrade. Second, the press release in 2025 used "up to" language: up to 15% speed, up to 30% power and more than 20% logic density. The 2026 call used ranges. Plan around the low end.
NanoFlex Pro: the standard cell change
NanoFlex is TSMC's standard cell architecture for nanosheets. It debuted on N2 and lets designers mix short, low-power cells with tall, high-performance cells inside the same block.
On A14, TSMC evolves it into NanoFlex Pro. Zhang called it design-technology co-optimization that lets designers "achieve optimum power performance benefit". TSMC hasn't published what changed at the cell level.
That's worth saying plainly. Nobody outside TSMC's customer base knows whether NanoFlex Pro adds finer-grained transistor choices, new cell heights or just better tooling. Tom's Hardware's own read was that TSMC had not disclosed explicit technical details separating the two.
What it means for you: if you're planning an A14 design, the cell library is where much of the 25% to 30% power gain in TSMC's range will be won or lost. Early PDK access matters more than the headline number.
Second generation nanosheets: what changes from N2
N2 was TSMC's first nanosheet node, and the move from FinFET to GAA is now in volume. TSMC said N2 entered high-volume manufacturing in the fourth quarter of 2025 with good yield, and that the N2 family's capacity will more than double in 2027.
A14 is the second generation of that transistor. TSMC's July 2026 call described it as "the second generation of nanosheet transistors" delivering "another full node stride from N2".
TSMC hasn't disclosed sheet count, sheet width or gate pitch for A14. The useful mental model is the one in Inside Deep Tech's TSMC 2nm full guide: N2 proved the device works at scale, and A14 is where TSMC starts shrinking it.
The density number is the tell. A14's 1.23x logic density gain over N2 is far larger than the 1.07x to 1.10x that A16 gets from backside power alone. Geometric scaling is still doing the heavy lifting.
Backside power: why A14 ships without it
The most misunderstood fact about A14 is that the base node has no backside power delivery. Zhang said at launch that "the first version of this technology does not have the backside power rail".
TSMC's logic is cost. Backside power adds wafer flipping, bonding and thinning steps. Phones and client chips that don't push huge currents don't need it, so they get A14 with a conventional front-side power network.
High-current AI and HPC chips do need it. In 2025 TSMC promised a version of A14 with backside power in 2029. At the 2026 symposium it named that version A12, described by Zhang as the next generation of Super Power Rail after A16.
Zhang also explained why A12 isn't just A14 plus a flip: "To continue shrinking the frontside geometry, you also need to scale the backside". Inside Deep Tech's backside power delivery full guide covers how Super Power Rail differs from Intel's PowerVia.
A13 and A12: the A14 family
TSMC now treats A14 as a platform. At the April 22, 2026 symposium it added two derivatives, both for 2029, and split the roadmap by market.
A13: an optical shrink for client chips
A13 is a direct shrink of A14. TSMC's July call put it at over 6% die area saving through a 97% optical shrink, with design rules backward compatible with A14 so customers can move IP with minimal redesign.
A12: Super Power Rail for AI and HPC
A12 brings Super Power Rail to the A14 platform. Tom's Hardware reports TSMC's new rule: a new client node every year, and a new AI and HPC node every two years, with A16 handing over to A12.
- Client track (annual): N2 (2025), then N2U and A14 (2028) and A13 (2029), per TSMC's 2026 roadmap.
- AI and HPC track (biennial): A16 (2027), A12 (2029), both with Super Power Rail, per the same roadmap.
SemiEngineering called A12 in 2029 an aggressive speedup in delivering a new technology node. That's fair. It's one year after A14 itself.
No High-NA EUV for TSMC A14
TSMC builds A14 on the same 0.33 NA EUV scanners it uses today. At its 2025 European symposium, Zhang said the A14 gains are "very substantial without using High-NA" and that TSMC will adopt it only when it gives "meaningful, measurable benefit".
In 2026 TSMC extended that to the whole roadmap. Tom's Hardware reported no plans to use High-NA EUV for any nodes through 2029, including A13 and A12.
That's a direct contrast with Intel, whose 14A introduces second-generation RibbonFET, PowerDirect backside power and High-NA EUV at once. For the scanner side of the story, read Inside Deep Tech's EUV lithography guide and High-NA EUV guide.
The tradeoff is multi-patterning. Asked whether A14 leans heavily on it, Zhang said he couldn't comment on specifics. More exposures per layer mean more steps, more cycle time and more cost per wafer.
TSMC A14 development status and timeline
TSMC's most specific A14 health check came on its July 16, 2026 earnings call. An internal product-like vehicle showed close to 90% device performance and close to 90% yield on a 256Mb SRAM, and customer tape-out activity was "ahead of schedule".
By the October 15, 2026 call, CEO C.C. Wei said TSMC had seen more customer activity on A14 than on 2nm so far.
- April 23, 2025: TSMC unveils A14 at its North America Technology Symposium, production planned for 2028.
- May 2025: Zhang says A14 won't use High-NA EUV.
- October 2025: TSMC files plans for the Taichung A14 fab, estimated at US$49 billion.
- April 22, 2026: TSMC adds A13 and A12 for 2029.
- July 1, 2026: Socionext announces an A14 compute chiplet with tape-out planned for September 2026.
- July 16, 2026: TSMC reports close to 90% 256Mb SRAM yield on A14 test vehicles.
- October 15, 2026: TSMC repeats risk production in 2027, volume in 2028.
- 2027 and 2028: Risk production, then volume production.
- 2029: A13 and A12 enter production.
Note the gap between "close to 90%" of target device performance and a shipping product. Test vehicle metrics are leading indicators, not product yields.
Fab 25 in Taichung: where A14 gets built
A14's home is a new fab complex in the Central Taiwan Science Park. TrendForce, citing Economic Daily News, reported a US$49 billion (NT$1.5 trillion) investment with groundbreaking planned for November 5, 2025, and four planned fabs that may all run 1.4nm.
Construction is moving fast. In July 2026 the science park's director said the first fab building should be complete before April 2027, with supply chain sources pointing to pilot production as early as 3Q 2027 and mass production by mid-2028.
TSMC itself has been careful. In September 2026 it reaffirmed 2028 for commercial A14 production after reports that the faster construction meant an earlier ramp. A finished building isn't a qualified line; EUV tool install and yield learning still take many months.
J.P. Morgan now models A14 mass production in the first half of 2028, with first revenue in the second half. Treat that as an analyst estimate.
Who will use TSMC A14
TSMC doesn't name node customers, and no chipmaker has announced a shipping A14 product. Here's what's actually on the record.
| Company | What's public | Status |
|---|---|---|
| Socionext | A14 compute chiplet, tape-out planned September 2026 | Confirmed by company |
| Apple | A22 Pro on A14 for 2028 iPhones | Reported, not confirmed |
| TSMC customer base | More A14 customer activity than N2 | TSMC statement, no names |
| Qualcomm, MediaTek | May stay on 2nm one more generation | Reported, not confirmed |
Source: Socionext press release (July 1, 2026); TSMC 3Q26 earnings call; Apple, Qualcomm and MediaTek reports summarized by The News, citing Bloomberg.
Socionext's chip is a platform to validate CPU and xPU architectures for AI hyperscale customers, not a product. It's still the first named A14 design, and it points to custom data center silicon as an early A14 user.
What TSMC A14 will cost
TSMC doesn't publish wafer prices. The most cited estimate puts an A14 wafer at about $45,000, against roughly $30,000 for an N2 wafer according to Digitimes, as summarized in the same report.
If that holds, A14 costs about 50% more per wafer than N2 for roughly 20% more chip density. Cost per transistor would rise, not fall. That's Inside Deep Tech's arithmetic from a reported estimate, so treat it as directional.
It's also why A13 matters. A design-compatible 6% shrink in 2029 lets a customer squeeze more dies from each costly wafer without a full redesign.
TSMC A14 vs Intel 14A vs Samsung SF1.4
All three foundries have a 1.4nm-class node on the roadmap. Their bets differ on backside power and lithography.
| Node | Transistor | Backside power | High-NA EUV | Volume target | Named external customer |
|---|---|---|---|---|---|
| TSMC A14 | 2nd gen nanosheet | No (A12 adds it in 2029) | No | 2028 | Socionext test chip |
| Intel 14A | 2nd gen RibbonFET | Yes, PowerDirect | Yes | 2028 | None announced |
| Samsung SF1.4 | GAA (MBCFET) | Not confirmed | No (High-NA from 1nm class) | 2029 | Talks disclosed, no names |
Source: Intel 14A via TrendForce (Sept 2026); Samsung SF1.4 roadmap via Tom's Hardware; Samsung 3Q26 call via Seoul Economic Daily; TSMC rows from Tom's Hardware.
Intel plans to release its 14A 0.9 PDK in October 2026, begin risk production in the second half of 2027 and ramp in 2028. That puts it on the same calendar as A14 for the first time in a decade. Inside Deep Tech's Intel 18A guide covers how Intel got here.
Samsung moved SF1.4 to 2029. On its October 29, 2026 earnings call it said it was in talks with multiple clients on 1.4nm and had confirmed development with some.
Inside Deep Tech's take
Inside Deep Tech expects A14 volume production to land in 2028 as promised. TSMC has hit its N2 date, kept the A14 numbers unchanged for a year and reported SRAM yield publicly. The open question isn't the schedule. It's price, and how many customers will pay for A14 instead of riding N2U.
Honest limits: where the TSMC A14 story can break
1. The numbers are TSMC targets
Every A14 gain figure is a TSMC projection against N2. Independent measurements on A14 silicon don't exist yet, and the 2025 "up to" figures were narrowed to ranges in 2026.
2. Few named customers
Socionext is the only company to name an A14 design publicly. TSMC's "more customers than N2" claim can't be checked from outside.
3. Cost per transistor
A reported wafer price about 50% above N2 for about 20% more density means many chips may not save money by moving. N2U exists for exactly that reason.
4. No backside power until A12
AI accelerators that need backside power can't use A14 itself. They wait for A12 in 2029 or use A16, which keeps first-generation nanosheets.
5. Multi-patterning instead of High-NA
Skipping High-NA saves scanner cost but adds exposures. If the extra patterning steps hurt yield or cycle time, the cost case gets worse.
What TSMC A14 means for you
- Chip designers: A14 is a new node with new IP. Budget for a full redesign, or use N2U for a cheaper 2028 refresh.
- AI accelerator teams: compare A16 in 2027 with A12 in 2029. A14 alone lacks backside power.
- Investors: watch the 2027 risk production update and named tape-outs, not fab construction headlines.
- Equipment buyers: A14 runs on 0.33 NA EUV, so it extends demand for today's scanners rather than High-NA.
FAQ
What is TSMC A14?
TSMC A14 is TSMC's 1.4nm-class logic process with second-generation nanosheet transistors and NanoFlex Pro cells. It's a full-node shrink from N2, due in volume production in 2028.
When will TSMC A14 be in production?
TSMC plans risk production in 2027 and volume production in 2028. The company repeated that schedule on its October 15, 2026 earnings call.
How much better is A14 than N2?
TSMC says A14 gives 10% to 15% more speed at the same power, or 25% to 30% less power at the same speed, with close to 20% more chip density. Those are TSMC targets from its July 2026 call, not independent measurements.
Does TSMC A14 have backside power delivery?
No. Base A14 uses front-side power. TSMC's Super Power Rail comes to the A14 platform as A12, scheduled for 2029.
Does TSMC use High-NA EUV for A14?
No. TSMC builds A14 with standard 0.33 NA EUV and has said it has no High-NA plans for any node through 2029.
Who are TSMC A14 customers?
Socionext is the only company that has publicly announced an A14 design. Apple is reported to plan its 2028 iPhone chip on A14, but neither Apple nor TSMC has confirmed it.
What to watch next
TSMC A14 has a clear date, stable targets and its first public tape-out. Three signals will show whether it becomes the big node TSMC promises: the 2027 risk production update, the first named smartphone or AI customer, and Intel's 14A yields against the same 2028 window.
For the node A14 replaces, read Inside Deep Tech's TSMC 2nm full guide. For the power delivery change A12 brings in 2029, read the backside power delivery full guide.
