TSMC 2nm (N2): A Full Guide to Nanosheets, N2P, A16, Customers, Capacity and Limits

TSMC 2nm went from a roadmap slide to a revenue line in three quarters. N2 entered high-volume manufacturing in the fourth quarter of 2025, and by the third quarter of 2026 it already made up 8% of TSMC's wafer revenue, up from 3% one quarter earlier. The catch: gross margin fell 1.3 points in the same quarter, mainly because of the 2nm ramp.

That tension between demand and cost runs through everything about TSMC's first nanosheet node. This full guide covers what N2 is, the whole 2nm family from N2P to A16, who actually ships on it, capacity and Arizona, how it stacks up against Intel 18A and Samsung SF2, and the honest limits, all as of October 19, 2026.

If you want the transistor physics first, Inside Deep Tech's GAAFET and nanosheet transistor guide explains the device itself. This guide stays on TSMC's node, its products and its business.

Last updated: October 19, 2026.

Key Takeaways

• TSMC 2nm (N2) is in volume production and reached 8% of TSMC's Q3 2026 wafer revenue.
• N2 promises 10% to 15% more speed or 25% to 30% less power than N3E, using TSMC's first nanosheet transistors.
• A16 adds Super Power Rail backside power, but volume production slipped from late 2026 to 2027.
• Shipping N2 chips include Apple's A20 Pro and AMD's EPYC Venice; TSMC expects N2 family capacity to more than double in 2027.
• Honest limit: N2 is made only in Taiwan today, and Taiwan's N-2 rule keeps the newest nodes at home.

What TSMC 2nm (N2) actually is

N2 is TSMC's first process that drops the FinFET for gate-all-around nanosheet transistors. TSMC confirms N2 entered high-volume manufacturing in the fourth quarter of 2025 with good yield, ramping in multiple phases at Hsinchu and Kaohsiung.

The headline numbers are TSMC's own, measured against N3E: 10% to 15% higher speed at the same power, or 25% to 30% lower power at the same speed, plus a 15% gain in chip density. TSMC's density figure is a mixed design of 50% logic, 30% SRAM and 20% analog, not pure logic.

Two things N2 does not have. It doesn't use High-NA EUV, and it doesn't use backside power delivery. Both matter later in this guide.

NanoFlex: why the design kit matters as much as the transistor

N2 is also TSMC's first node to use NanoFlex, which lets designers mix short, power-efficient cells and tall, high-performance cells in the same block. That's how one node can serve a phone chip and a large server CPU without two separate processes.

Here's why that matters to you. A node's value isn't only its transistor. It's how many products can reuse the same IP, and NanoFlex is TSMC's bet that N2 will be a long-lived, multi-market node.

The TSMC 2nm family at a glance

N2 is not one process. It's a platform with a client track that updates every year and an AI and HPC track that updates every two years, a split TSMC formalized at its April 2026 symposium.

Source: TSMC figures compiled by Tom's Hardware from the 2025 and 2026 Technology Symposiums, and TSMC's Q3 2026 earnings call. Density is TSMC's mixed chip density.

Read the table in two directions. Down the rows, each step is smaller than the last, which is what a maturing platform looks like. Across the A16 row, the big jump is power, which is exactly what AI racks need.

N2P, N2X and N2U: the client track

N2P is the volume workhorse for 2026 and 2027 flagship phones. MediaTek, one of the first N2P customers, says that against N3E it offers as much as 18% more performance at the same power, about 36% less power at the same speed and 1.2x logic density.

N2X pushes clocks for designs that want maximum frequency on front-side power. N2U arrives in 2028 and keeps N2P IP compatibility while adding 3% to 4% speed or 8% to 10% lower power, a cheap upgrade path rather than a new node.

The point of the client track is IP reuse. A company that builds a premium N2P chip in 2027 can reuse that work on N2U the following year without paying for an all-new design.

A16 and Super Power Rail: the AI track

A16 is, to a large degree, N2P with backside power. TSMC's Super Power Rail connects the backside power network directly to each transistor's source and drain, the most complex and costly form of backside power, and the one that frees the most front-side routing.

Against N2P, TSMC quotes 8% to 10% more speed, 15% to 20% less power and 1.07x to 1.10x density. For a large AI accelerator, the power figure is the one that changes rack economics.

The schedule moved. TSMC first targeted A16 volume production in the second half of 2026. At the April 2026 symposium, Kevin Zhang said the process would be ready in 2026, but actual product ramp depends on customers, so volume production is now listed for 2027.

Backside power isn't for everyone. Asked on the Q3 2026 call whether power-grid limits would push more customers to Super Power Rail, C.C. Wei said the choice depends on each product: some accelerators may use it, and phones don't. Inside Deep Tech's backside power delivery guide compares Super Power Rail with Intel PowerVia and Samsung's plans in detail.

Who is actually on TSMC 2nm

TSMC says N2 has had the strongest customer adoption of any node, with more than 20 tape-outs received and over 70 in the pipeline as of April 2026. Here are the products with public confirmation, plus the reported ones, labeled as such.

Source: company press releases from Apple, AMD and MediaTek; the last two rows are press reports compiled by TrendForce, not confirmed by the companies.

Apple A20 Pro: the first 2nm iPhone chip

Apple's A20 Pro is built on 2-nanometer technology, with a GPU up to 40% faster than A19 Pro and 50% more memory bandwidth. Apple also placed the memory beside the die so the chip can attach directly to a new vapor chamber, a reminder that a new node alone doesn't fix sustained performance in a phone.

AMD EPYC Venice: the first HPC product on N2

AMD taped out Venice as the first HPC product on N2 in April 2025 and announced its production ramp in Taiwan in May 2026, with plans to ramp later at TSMC Arizona. That's the clearest proof that N2 isn't only a phone node.

Notice who is missing from the confirmed list. As of October 19, 2026, NVIDIA hasn't publicly confirmed a data center GPU on N2. For AI accelerators, the tighter constraint is often packaging rather than the node, which is why Inside Deep Tech's TSMC CoWoS guide is the companion read to this one.

Capacity, fabs and money

Demand is the easy part. TSMC said on October 15, 2026 that it expects N2 family annual capacity to more than double in 2027, and the company reiterated a 2026 capital budget of $60 billion to $64 billion.

• Revenue: 2nm went from 3% of wafer revenue in Q2 2026 to 8% in Q3 2026, when 3nm still made up 33%.
• Margin: Q3 gross margin was 66.4%, down 1.3 points, mainly from 2nm ramp dilution. Q4 guidance is $52.3 billion to $54.3 billion in revenue.
• Taiwan fabs: N2 is ramping at Hsinchu and Kaohsiung, the only N2 production sites today.
• Arizona: TSMC added $100 billion in July 2026, for a total U.S. commitment of $265 billion, and plans N2 and A16 production in Arizona.

Arizona matters, but not yet for N2. TSMC's second Arizona fab, an N3 fab, begins volume production in Q3 2027. The N2 and A16 fab comes after it, and TSMC is also evaluating further expansion in Texas.

That means every N2 wafer shipped in 2026 came from Taiwan. If your supply plan assumes U.S.-made 2nm chips before the late 2020s, it's ahead of TSMC's own schedule.

TSMC 2nm vs Intel 18A vs Samsung SF2

All three leading-edge foundries now ship gate-all-around transistors. They made different bets on backside power and on who their customers are.

Source: Tom's Hardware on N2 versus 18A power delivery, Inside Deep Tech's Intel 18A guide and Samsung's Exynos 2600 page, which calls it the industry's first 2nm GAA chip.

Intel shipped backside power first, and Samsung shipped a 2nm-class GAA phone chip first. TSMC shipped the node with the broadest list of outside customers. For a fabless chip company, that last point usually decides where the design goes.

No High-NA EUV, by design

TSMC is building N2, A16 and even its 2029 nodes without High-NA EUV. Its April 2026 roadmap shows A13 and A12 in 2029 on standard EUV, with no High-NA tools, and on the Q3 call management pointed to High-NA adoption around 2030.

That's a cost decision. Inside Deep Tech's High-NA EUV guide explains why a single High-NA scanner costs far more than a standard EUV tool, and why TSMC prefers multi-patterning and design co-optimization until the economics flip.

For how the standard EUV scanners behind N2 work, and why ASML is the only company that sells them, see Inside Deep Tech's EUV lithography full guide.

TSMC 2nm timeline, 2025 to 2029

• April 2025: AMD tapes out EPYC Venice, the first HPC product on N2.
• September 2025: MediaTek tapes out its first N2P flagship chip.
• Q4 2025: N2 enters high-volume manufacturing in Hsinchu and Kaohsiung.
• December 2025: Taiwan reaffirms the N-2 rule for overseas fabs.
• April 2026: TSMC adds N2U, A13 and A12 and moves A16 volume production to 2027.
• May 2026: AMD starts the Venice production ramp.
• July 2026: TSMC lifts its U.S. commitment to $265 billion.
• September 2026: Apple ships the A20 Pro in iPhone 18 Pro.
• October 2026: 2nm hits 8% of wafer revenue, and TSMC guides to more than double N2 family capacity in 2027.
• 2027 to 2029: A16 and N2X in 2027, A14 and N2U in 2028, A13 and A12 in 2029, per TSMC's roadmap.

The cadence is the message. TSMC now ships something new on the 2nm platform every year, so a single "2nm" label will cover very different chips by 2028.

The honest limits of TSMC 2nm

First, geography. N2 is produced only in Taiwan today, and Taiwan's government says only technology two generations behind TSMC's most advanced domestic process may go overseas. The rule caps how close Arizona can get to the leading edge.

Second, the schedule for the AI-specific node slipped. A16 moved from late 2026 to 2027 volume production, so the first big backside-power accelerators from TSMC arrive later than the 2025 roadmap implied.

Third, cost. TSMC doesn't publish wafer prices, but its own numbers show the strain: the 2nm ramp is the main reason Q3 gross margin fell 1.3 points. New nodes get cheaper with yield learning, but N2 is not a cheap node and won't become one in 2027.

Fourth, supply is tight. Press reports in early 2026 said 2nm capacity was fully booked, with Apple reportedly taking much of the first output. If you're a smaller design house, your N2 slot may be years out.

Fifth, IP security. Taiwan's Supreme Court made final a 10-year sentence for a former TSMC engineer who stole 2nm-related trade secrets for Tokyo Electron Taiwan, which was ordered to pay NT$100 million in compensation to TSMC. Tokyo Electron said it found no evidence of leakage to third parties.

Sixth, the PPA numbers are TSMC's own. Independent, die-level comparisons of N2 against 18A and SF2 are still scarce, and mixed-density figures flatter nodes with strong SRAM scaling.

Inside Deep Tech's take

Who should care most? If you design chips, plan N2P or N2U for client products and treat A16 as a 2027 to 2028 option for only the most power-hungry dies. If you invest, watch 2nm's share of wafer revenue and the gross margin line together. If you buy servers, AMD Venice is the first chance to buy 2nm silicon in a data center.

What to watch next

• TSMC's Q4 2026 results in January 2027: does 2nm's share keep climbing from 8% in Q3, and does margin recover?
• N2P product launches from MediaTek and other flagship phone chipmakers in late 2026 and early 2027.
• Any named A16 customer, and whether the 2027 volume production date holds.
• Progress on the Arizona N2 and A16 fab and any decision on Texas.
• A14 risk production in 2027, with volume production in 2028.

FAQ

The bottom line

For the next two years, TSMC 2nm is where the industry's flagship phones, server CPUs and next AI accelerators converge. If you're planning a chip, a server refresh or a portfolio around it, track three dates: N2P phone launches in late 2026, A16 volume production in 2027 and the first Arizona 2nm wafers after that.

For the transistor underneath all of it, read Inside Deep Tech's GAAFET and nanosheet transistor guide next.

GAAFET and Nanosheet Transistors: A Full Guide (2026)

How gate-all-around nanosheets work, why FinFET ran out of room, and how TSMC N2, Intel 18A and Samsung SF2 compare.

Inside Deep Tech