CFET stacks nFET and pFET into one footprint after GAAFET: Samsung's 42 nm gate-pitch 2026 VLSI Best Paper, imec's A7 / ~2033 commercial call, mCFET vs sCFET, and why volume chips still wait.
AECs put DSP retimers in copper OSFP/QSFP-DD assemblies for AI scale-out: Credo ZeroFlap 800G SPAN to 7 m, Marvell Alaska A 1.6T beyond 3 m, and why DAC, ACC, AOC, and CPO are different BOM columns.
SOCAMM puts LPDDR5X on detachable compression modules for NVIDIA Vera: up to 1.2 TB/s and 1.5 TB, JEDEC JESD328 SOCAMM2 in June 2026, and why many racks ship 96 GB modules instead of 192 GB.
MRDIMM (Multiplexed Rank DIMM) doubles the bytes per cycle on server DDR5 by muxing two ranks through on-DIMM MRCD and MDB buffers. Gen1 ships near 8800 MT/s on Intel Xeon 6 versus RDIMM 6400, with JEDEC Gen2 raw cards targeting 12,800 MT/s.
Everything you need to understand GDDR7 in 2026: JEDEC JESD239 PAM3 signaling, up to 192 GB/s per device, Micron and Samsung shipping speeds, how RTX 50 and Rubin CPX use it, and why board-level GDDR is not a substitute for HBM on an interposer.
Everything you need to understand PCIe 6.0 in 2026: 64 GT/s PAM4, 256 GB/s x16, FLIT mode, FEC/CRC, L0p power, how it differs from NVLink and NVLink-C2C, where Blackwell still uses Gen6 for NICs and host attach, and why PCIe is not the GPU-to-GPU fabric.
Everything you need to understand how AI GPUs talk in 2026: why NVLink is scale-up and InfiniBand is scale-out, where Ultra Ethernet and UALink fit, and why treating them as substitutes is the expensive mistake.
Everything you need to understand hybrid bonding in 2026: why microbumps ran out of pitch, how Cu-Cu bonding works, TSMC SoIC vs Intel Foveros Direct, face-to-face density, and why 3D stacking is now a volume technology.
Everything you need to understand 800 VDC in 2026: why 48/54 V bus bars run out of copper at 100–120 kW, NVIDIA’s Kyber architecture, facility MV-to-rack conversion versus 415/480 VAC, who actually ships, and why this is a 2027 hall not a 2026 BOM.
Everything you need to understand High-NA EUV in 2026: 0.55 vs 0.33 NA, anamorphic 4×/8× optics, 8 nm vs 13 nm, EXE:5000/5200B, Intel’s 18A beachhead, TSMC’s Low-NA bet, and why most chips still print on 0.33.
Everything you need to understand backside power in 2026: why front-side grids ran out of room at GAAFET pitches, how BSPDN (buried rails, nano-TSVs, backside metal) works, Intel PowerVia vs TSMC Super Power Rail vs Samsung SF2Z, and what ships versus slides.
Everything you need to understand glass core substrates in 2026: why ABF organic cores warp as CoWoS packages grow, what a through-glass via is, Intel’s EMIB-on-glass demos versus Absolics samples, and why this is not CoWoS.
Everything you need to understand Compute Express Link in 2026: CXL.io vs CXL.cache vs CXL.mem, Type 1/2/3 devices, pooling vs sharing vs tiering, why AI servers care, and why Type-3 cards ship while a general CXL fabric does not.
Everything you need to understand TSMC CoWoS in 2026: CoWoS-S vs CoWoS-L vs CoWoS-R, why NVIDIA, AMD, and Broadcom fight for allocation, and why the assembly slot — not the transistor node — gates AI GPUs.
Everything you need to understand why 2026 leading-edge logic wraps the gate around the channel: why FinFET ran out of room, how a nanosheet GAAFET works, Intel 18A / TSMC N2 / Samsung SF2, backside power, and what angstrom marketing does not mean.
Everything you need to understand why 2026's biggest chips are no longer one piece of silicon: the reticle limit, chiplet economics, proprietary fabrics versus the UCIe standard, and why mix-and-match dies remain more aspiration than product.
Everything you need to understand why AI racks in 2026 need water, not just air: direct-to-chip cold plates, coolant distribution units, rear-door heat exchangers, immersion, and the facility-water classes that decide whether a hall can host a 120 kW rack.
Everything you need to understand the light that prints every leading-edge chip in 2026: how a tin-plasma EUV machine works, Low-NA versus High-NA, who can buy one, and why the scanner is as much of a bottleneck as the silicon.
