GAAFET and Nanosheet Transistors: A Full Guide to How Chips Leave FinFET Behind

A gate-all-around field-effect transistor is not a smaller FinFET. It is a different geometry: the channel is a stack of thin silicon sheets, and the gate oxide and metal wrap every sheet on all four sides. The product the customer buys — a laptop CPU, a phone SoC, later a server die — still looks like a chip. The thing that switched is the device that prints under EUV.

That switch exists because the alternative ran out of electrostatics. A FinFET gates three sides of a vertical fin. It was the right answer from Intel's 22 nm Tri-Gate in 2011 through TSMC's entire 3 nm family. As contacted-poly pitch stalled near 45–50 nm and fins got taller and thinner, short-channel control, width quantization, and parasitic capacitance stopped paying for the next shrink. SRAM bitcells, which had been the density trophy of every node, barely moved.

What changed in 2026 is not that GAAFET was invented. Research nanosheets are a decade old. It is that three foundries are now shipping production GAA logic at once — TSMC N2 nanosheets in volume since 4Q 2025, Intel 18A RibbonFET plus PowerVia in Panther Lake PCs, Samsung SF2 MBCFET on captive mobile silicon — while backside power, the other half of the "angstrom" pitch, is only in high volume at Intel. The useful question is which of those nodes is a purchase order, which is a process family still ramping, and what the name "18A" or "N2" does not tell you about gate length.

Key takeaways

• A GAAFET wraps the gate around a stacked nanosheet channel. It is not a 2 nm-long transistor. Channel length still sits in the tens of nanometers. The sheets are a few nanometers thick. "2 nm" and "18A" are node names. Intel's own 18A-P disclosure puts contacted poly pitch at 50 nm.
• FinFET died of electrostatics and quantization, not of marketing. Three-sided control and integer fin counts were enough through 3 nm. They were not enough for the next full node of leakage, drive, and SRAM Vmin.
• TSMC N2, Intel 18A, and Samsung SF2 are the same idea with different risk budgets. TSMC put first-generation nanosheets into volume in 4Q 2025 and left backside power for A16. Intel shipped RibbonFET and PowerVia together on 18A. Samsung put MBCFET into production first, at 3 nm, and is on its second GAA generation at 2 nm-class.
• Backside power is a routing decision, not a transistor. PowerVia and TSMC's Super Power Rail move the power grid to the wafer's back so the front side can carry signals. Intel's VLSI 2026 numbers — 11% routed-area cut, 10× lower dynamic voltage droop — are why 18A is not "just GAA."
• 2026 AI GPUs are still mostly FinFET plus HBM and advanced packaging. N2 and 18A are ramping in phones and PCs, with HPC/AI following as yield and capacity allow. GAA is the next logic node. It is not yet the volume accelerator node.
• Yield and SRAM density decide whether the node is a business. A working nanosheet on a test chip is not a 300 mm line filling CoWoS. Treat foundry PPA slides as design targets. Treat defect density, bitcell Vmin, and wafers per month as the product.

GAAFET at a glance

What a GAAFET actually is

Start with the thing it is not. It is not a new kind of lithography. EUV still prints the patterns; High-NA is a later tool, not a requirement for first-generation nanosheets. It is not a chiplet. Chiplets are how you partition a product across dies. GAAFET is how you build the transistors on one of those dies. And "angstrom-era process" on a slide does not tell you whether the power grid is on the front, the back, or still a PowerPoint.

A planar MOSFET, the device of the 1980s through roughly 28 nm, had a gate sitting on top of a flat channel. When the gate got short, it lost control of the silicon underneath. The FinFET stood the channel on edge: a thin vertical fin, gate covering the top and two sidewalls. Intel branded it Tri-Gate at 22 nm. TSMC took fins from 16 nm through N3. Three-sided control bought about a decade of scaling.

A gate-all-around nanosheet FET lies the channel back down, then stacks it. Two, three, or four thin silicon sheets sit one above another, separated by the gate metal that wraps each sheet completely. The wrap is the electrostatic win: there is no ungated bottom. The stack is the drive-current win: effective width is sheet count times sheet width, without growing the cell's footprint the way a fourth fin would. The tunable width is the design win FinFET never had. You cannot have 1.7 fins. You can have a 15 nm-wide sheet in a dense cell and a 40 nm-wide sheet in a high-performance cell on the same wafer. TSMC markets that as NanoFlex. Samsung's MBCFET (Multi-Bridge-Channel FET) is the same stacked-sheet idea under a trademark. Intel's RibbonFET is the same idea with a ribbon-shaped channel and, on 18A, a backside power network attached through nano-TSVs.

Three neighboring devices get flattened into "GAA" in vendor copy. They are not the same product.

Nanosheet / RibbonFET / MBCFET. Horizontal stacked sheets, production 2025–2026. This is what N2, 18A, and SF2 actually ship.

Nanowire. A round or square wire instead of a wide sheet. Better electrostatics, worse drive current per footprint. Research and some early Samsung 3 nm talk used "nanowire" language; volume 2 nm-class logic is sheets, not wires.

Forksheet and CFET. Next architectural bets. Forksheet puts n- and p-devices closer by sharing a dielectric wall. Complementary FET (CFET) stacks nFET on pFET (or the reverse) to cut inverter area. Intel showed monolithic CFET inverters at a 45 nm gate pitch at VLSI 2026. That is a path after GAA, not a 2026 SKU.

Why FinFET ran out of room

The physics is not exotic. A short gate has to control the whole channel or the device leaks when it is supposed to be off. Subthreshold swing and DIBL (drain-induced barrier lowering) are the numbers. Fins helped until the remaining ungated bottom, the parasitic capacitance of a tall thin fin, and the contact resistance of a skinny source/drain stopped the next shrink from being free.

Width quantization is the design problem people skip. Drive current in a FinFET comes in integer fins. Standard-cell libraries became a menu of 2-fin and 3-fin devices, which is why TSMC's FinFlex on N3 existed: mix fin counts in one block. It was a workaround for a quantized device. Nanosheet width is set by lithography and etch, not by counting fins, so the library can target drive current continuously. That is a real PPA lever. It is also a process-control problem: sheet width and thickness variation show up directly as threshold-voltage scatter.

SRAM is the other FinFET failure mode. A 6T bitcell wants matched, low-leakage transistors at low Vmin. Late FinFET nodes improved logic density faster than they shrank the bitcell. Caches stopped being a free density gift. Every AI accelerator and CPU still pays for SRAM in area and in inference energy; a node that cannot move the bitcell is a node that only helps the logic half of the die. GAA's pitch is better channel control at low voltage, which is exactly where SRAM read/write margins die.

None of that required a new marketing unit. It required a four-sided gate and a stack.

How a nanosheet transistor is actually built

A working GAAFET is a process-integration object, not a cartoon of a wrapped wire. The sequence that matters on 300 mm:

1. Superlattice. Epitaxial Si / SiGe stacks define the future sheets (Si) and the sacrificial layers (SiGe). Sheet count is frozen here. Three sheets is a common production target; four is a density/performance knob.
2. Dummy gate and inner spacers. A replacement-gate flow still exists. Inner spacers, formed after a controlled SiGe recess, keep the later metal gate from shorting into the source/drain. This is one of the yield-critical etches.
3. Source/drain epitaxy. Raised, often SiGe for PMOS and Si:P or similar for NMOS, with the strain engineering Intel's 18A-P materials still talk about.
4. Channel release. The SiGe is etched out so the silicon sheets are suspended. Selectivity of that etch — 100:1 SiGe:Si is the kind of number process teams brag about — decides whether the sheet survives.
5. High-k / metal gate wrap. Gate dielectric and work-function metals fill around every sheet. Work-function tuning, not just lithography, sets the multiple Vt options a library needs. Intel 18A-P added a fifth logic Vt pair between ULVT and LVT for exactly this reason.
6. Contacts, middle-of-line, then either a frontside power grid or a wafer flip for backside power.

That last fork is the 2026 differentiator. TSMC N2 still powers from the front, with a super-high-performance metal-insulator-metal capacitor in the power network as the conservative upgrade. Intel 18A flips the wafer, reveals the transistor from the back, and lands PowerVia. Samsung's first 2 nm (SF2) is frontside; SF2Z, the backside variant, was roadmapped at the 2024 Foundry Forum for mass production in 2027.

EUV layer count on N2 is in the same band as N3E. First-generation GAA does not wait for High-NA. High-NA is a later overlay and pitch tool, not the thing that makes a nanosheet wrap.

Backside power: PowerVia, Super Power Rail, and what actually changed

In a conventional chip, the metal stack above the transistors carries both signals and power. Those two jobs fight for the same tracks. Power wants fat, low-resistance lines. Signals want density. At low voltage the fight shows up as IR drop and dynamic droop: the transistor did not get the voltage the SPICE deck assumed.

Backside power delivery (BSPDN) moves the power grid to the back of the wafer. Signals keep the front. A nano-scale through-silicon via in the cell, or a buried power rail plus backside contact, connects the device to that grid. Intel's production name is PowerVia. TSMC's production name, on A16, is Super Power Rail. Samsung's is BSPDN on SF2Z.

Intel is the only company that put this into a 2026 client product. At VLSI 2026, Intel Fellow Eric Karl quantified the foundry's backside-plus-GAA stack against a comparable frontside interconnect: 11% routed-area reduction and 10× lower dynamic voltage droop, which the company translates as up to 6% frequency or more than 15% dynamic power. Manju Shamanna's silicon talk at the same meeting reported about 30% frequency improvement at ~0.5 V on CPU cores built with GAA and backside power. Those are Intel measurements of Intel silicon, not a three-foundry bake-off. They are still the cleanest public accounting of why 18A is two innovations, not one.

TSMC split the risk. N2 is GAA without backside power. A16 is N2P-class nanosheets plus Super Power Rail, aimed at HPC designs with dense power grids. TSMC's VLSI 2026 A16 abstract (paper T1.5) put the claim at 8–10% higher speed at the same power, or 15–20% lower power at the same speed, plus 8–10% chip-density gain versus N2P, with mass production slated for Q4 2026. Kevin Zhang later told the 2026 North American Technology Symposium that A16 would be ready in 2026 and that actual product ramp depends on customers, with volume production expected in 2027. Both statements can be true: a process can be qualified in one year and fill a fab the next. Treat 2026 as A16 process readiness, not as a year of A16 AI GPUs.

PowerVia is not free. Wafer thinning, backside lithography, nano-TSV yield, and thermal paths through a thinned die are new defect modes. That is why TSMC did not put SPR on the first N2 mobile wave, and why Samsung parked backside power at SF2Z rather than on the first SF2 Exynos.

What "angstrom" marketing does and does not mean

Intel's node names jumped from nanometers (Intel 7, Intel 4, Intel 3) to angstroms (18A, 14A). 18 angstroms is 1.8 nm. TSMC's A16 is a 1.6 nm-class name. Neither number is the physical gate length, the nanosheet thickness, or the metal pitch.

The numbers that describe a logic process are still the old ones:

A 50 nm contacted-poly pitch is not a failure of 18A. It is the honest geometry. FinFET CPP had already slowed into this band. GAA's job is to make a 50 nm-pitch device that still controls the channel at 0.5–0.7 V, not to print an 1.8 nm gate. Anyone quoting "2 nm transistors" as a physical length is reading the brochure, not the design rule.

The same caution applies to density. Intel's Panther Lake announcement put 18A at up to 15% better performance per watt and 30% improved chip density versus Intel 3. TSMC's 2022 North America Technology Symposium put N2 at 10–15% speed at the same power, or 25–30% power at the same speed, versus N3, later restated against N3E. Samsung's 2023 Foundry Forum put SF2 at 12% performance, 25% power-efficiency, and 5% area versus SF3. Those are vendor PPA claims on vendor reference designs. They are not interchangeable, and they are not SRAM density.

The three production GAA nodes, compared

Samsung was first to put GAA into a fab, on 3 nm in 2022. That matters for process learning. It does not mean SF2 is the 2026 share leader. TSMC stayed on FinFET through N3E/N3P, which is why most 2025–2026 flagship phones and almost all AI accelerators were still FinFET, and why N2's job in 2026 is to take the next full node without taking backside power at the same time. Intel took both risks on one node and used its own CPU roadmap as the first customer — the IDM privilege TSMC does not have and that Intel Foundry still has to sell to someone else.

What actually shipped

TSMC N2: GAA without the second miracle

TSMC's N2 technology page is unusually blunt: volume production started in 4Q 2025 as planned, first-generation nanosheet, full-node strides in performance. That is the fact to start from. The 2022 symposium PPA (10–15% / 25–30%) is the design target the company has not walked back. N2P is the performance/power extension, scheduled through 2026. N2X keeps frontside power for designs that want clock speed more than routing relief.

What N2 is not, in August 2026: the default die inside a shipping NVIDIA or AMD flagship GPU. Those products remain chiplet packages on earlier TSMC nodes, married to HBM on CoWoS. TSMC has said the 2026 N2 ramp is fueled by smartphones and HPC/AI. That is a foundry-mix statement, not a SKU list. AI chip startups chasing a 2 nm-class tape-out still discover that a nanosheet PDK is easier to get than a CoWoS slot.

Intel 18A: two innovations, one captive CPU

Panther Lake — Intel Core Ultra Series 3 — is the existence proof. The 9 October 2025 architecture reveal called it the first client SoC on 18A, with high-volume production at Fab 52 in Chandler, Arizona, and broad availability from January 2026. CES 2026 was the commercial debut. The same briefing previewed Xeon 6+ (Clearwater Forest) as the first 18A server CPU: up to 288 E-cores, 17% IPC over prior generation, launch window first half of 2026.

18A versus Intel 3, in Intel's words: up to 15% better performance per watt, 30% improved chip density. RibbonFET is the transistor. PowerVia is the power grid. Foveros still stacks the chiplets. The process is not a monolith; the 18A tile is the new device sitting in a package Intel already knew how to assemble.

18A-P, the performance follow-on, entered risk production on 16 June 2026: 9% higher performance at iso-power or 18% lower power at iso-performance versus 18A, same 50 nm CPP, same 180/160 nm cell heights, design-rule compatible. Risk production is not high volume. It is the stage at which you run customer-like silicon before you promise a ramp. External foundry commitments remain the open commercial question; 18A's 2026 volume is Intel's own CPUs.

Samsung SF2: GAA from the company that went first

Samsung's MBCFET has been in production since 3 nm. The 2023 Foundry Forum put SF2 at 12% performance, 25% power efficiency, and 5% area versus SF3, with mobile mass production in 2025, HPC in 2026, automotive in 2027. The 2024 Forum added SF2Z with backside power, mass production slated for 2027.

The 2026 picture is a captive mobile wave plus a foundry that is still being asked, by every external customer, whether 2 nm yield is a business. Public yield percentages circulating on blogs are not measurements you can put in a bill of materials. What you can say from primary sources: Samsung has more years of GAA manufacturing than TSMC or Intel, its first 3 nm generation was widely reported as yield-limited, and SF2's job is to turn that learning into a node outsiders will tape out. Taylor, Texas, is a 2027 customer-production story, not a 2026 wafer story.

Yield, SRAM, and the density that actually matters

Logic PPA slides are easy. SRAM macros and defect density are the node.

A GAA sheet has more surfaces to damage, a channel-release etch that can undercut or leave residues, inner spacers that can close up, and a wrap metal that has to fill every gap. Early-time yield on that flow is why Samsung's first GAA generation was painful and why TSMC's decision to keep N3 as FinFET looks conservative only in hindsight. "Good yield" on an earnings call is not a D0 you can compare across companies. Treat any unsourced "N2 is at 70%" figure as noise.

SRAM is the measurable proxy. TSMC's IEDM 2024 N2 paper is the one public bitcell that is specific: a high-density cell of 0.0175 µm², about 38 Mb/mm², against roughly 32 Mb/mm²-class HD cells on N3E. The point is not the integer. It is that SRAM started moving again. GAA's low-voltage electrostatics is why: TSMC reported tens of millivolts of Vmin relief on HD and HC macros versus FinFET, with functional read/write toward ~0.4 V. That is how you put more cache on a CPU tile or more on-die SRAM next to an accelerator without the array dominating the floorplan.

Caches still do not replace HBM. A 38 Mb/mm² array on a 400 mm² die is tens of megabytes, not tens of gigabytes. GAA helps the logic and the on-die memory wall. The package memory wall is still stacks, an interposer, and whoever got the CoWoS allocation.

What is real and what is hype

Real

• GAA nanosheets are in production at all three leading-edge foundries in 2026. This is not a research topic.
• Four-sided electrostatic control and tunable sheet width are the physical reasons, not a slogan.
• Intel shipped GAA and backside power in the same client CPU. TSMC shipped GAA first and backside power later. Those are different, defensible risk orders.
• Contacted poly pitch on 18A-P is 50 nm. Node names are not lengths.
• SRAM bitcells started scaling again on N2, which is the first material cache-density news in several FinFET nodes.

Hype

• "2 nm transistors are 2 nm long." They are not. CPP, metal pitch, and sheet thickness are the geometry. 18A is a name.
• "GAA replaces EUV / High-NA / chiplets / HBM." GAA is the device. EUV prints it. Chiplets partition the product. HBM is the memory. You still need all four.
• "Every 2026 AI GPU is on GAA." Volume training silicon in 2026 is still overwhelmingly FinFET on TSMC N4/N3-class nodes, packaged with HBM. N2/18A/SF2 are ramping into HPC, not replacing the installed accelerator base this year.
• "Backside power is on every 2 nm chip." It is on Intel 18A. It is not on TSMC N2. It is not on Samsung SF2. A16 and SF2Z are the backside follow-ons, with product volume in 2027 unless a named customer ramps earlier.
• "CFET is next year's node." Intel's 45 nm-pitch CFET inverter is a VLSI 2026 research result. It is the architecture after GAA, on a timeline measured in nodes, not quarters.

A realistic timeline

One useful heuristic: ask which device (nanosheet, ribbon, MBCFET), whether power is front or back, what the contacted-poly pitch is, and whether the die in the product is actually on that node. Do not ask whether the company has "entered the angstrom era."

The bottom line

2026 is the year the logic transistor stopped being a fin.

The physics is old. Short gates need four-sided control. Stacked sheets restore width without restoring quantization. Backside power is a separate, optional bet on the metal stack. TSMC took the transistor first. Intel took the transistor and the power grid together and used its own CPUs as the pilot line. Samsung took GAA earliest, paid the 3 nm tuition, and is selling the second generation into a foundry market that still remembers the first.

For anyone making decisions today, the split is clean. If the question is what is inside a 2026 flagship phone or a Panther Lake laptop, you are looking at a nanosheet GAAFET, probably still frontside-powered unless the badge says 18A. If the question is what is inside a 2026 training GPU, you are still looking at FinFET logic, HBM, and a 2.5D package — with GAA in the foundry queue behind them. If the question is whether a vendor's "2 nm" or "18A" story is real, ask for the contacted-poly pitch, the backside-power yes/no, the SRAM bitcell, and the name of the product that already came off that line. The node name will not answer it.

Frequently asked questions

What is a GAAFET?

A gate-all-around FET is a transistor whose gate dielectric and metal fully surround the channel. In 2026 production, that channel is a stack of horizontal silicon nanosheets (TSMC), ribbons (Intel RibbonFET), or bridges (Samsung MBCFET). The wrap improves electrostatic control compared with a FinFET, which gates only three sides of a vertical fin.

How is a nanosheet different from a FinFET?

A FinFET's channel stands up; width comes in whole fins. A nanosheet's channel lies flat and stacks; width is a continuous design knob and drive current scales with sheet count. The process is harder (channel release, inner spacers, wrap fill). The device is better at low voltage, which is why SRAM and efficiency curves move.

What does Intel 18A actually include?

Two production innovations: RibbonFET GAA transistors and PowerVia backside power delivery, at a 50 nm contacted-poly pitch on 18A-P. Panther Lake (Core Ultra Series 3) is the first client product; Xeon 6+ Clearwater Forest is the first server product. 18A-P is a design-rule-compatible performance enhancement that entered risk production in June 2026.

Is TSMC N2 in volume production?

Yes. TSMC's N2 page states volume production started in 4Q 2025 as planned. 2026 is the ramp year, with N2P as the follow-on and A16 (nanosheet plus Super Power Rail) process-ready for HPC, with product volume weighted to 2027 on TSMC's own customer-ramp language.

Did Samsung really ship GAA first?

Yes, at 3 nm (MBCFET) in 2022. First is not the same as highest share or best yield. SF2 is the 2 nm-class continuation of that architecture. Backside power is on SF2Z, targeted for 2027 mass production, not on the first SF2.

Does "18 angstroms" mean the transistors are 1.8 nm long?

No. It is a node name. The physical pitches Intel has disclosed for 18A-P are a 50 nm contacted-poly pitch and 180/160 nm cell heights. Gate length, sheet thickness, and metal pitch are separate design rules. Treat any "2 nm transistor" claim that implies a 2 nm channel as marketing.

Will GAAFET cut the cost of running AI?

It can improve performance per watt on the logic die, which matters at 0.5–0.7 V and in on-die SRAM. It does not add HBM capacity, CoWoS supply, or cheaper energy at the wall. Inference TCO in 2026 is still dominated by memory bandwidth, utilization, and power delivery to the rack. GAA is a transistor. It is not a cluster.

What comes after nanosheets?

Forksheet-style n/p packing, then CFET — stacking nFET and pFET vertically. Intel's VLSI 2026 monolithic CFET inverter at 45 nm gate pitch is the public research marker. That is the device generation after GAA, not a 2026 process you can tape out for a GPU.

Methodology

This guide is based on primary foundry and device disclosures available as of 18 August 2026: TSMC's N2 technology page (volume production 4Q 2025, first-generation nanosheet transistors); TSMC's 16 June 2022 North America Technology Symposium N2 PPA (10–15% speed at iso-power or 25–30% power at iso-speed versus N3, nanosheet architecture, production then scheduled for 2025); TSMC VLSI 2026 paper T1.5 on A16 Super Power Rail (8–10% speed or 15–20% power versus N2P, 8–10% density, Q4 2026 mass-production target) and TSMC's 2026 symposium language that A16 is process-ready in 2026 with product volume expected in 2027; Intel's 9 October 2025 Panther Lake architecture announcement (first 18A client SoC, up to 15% PPW and 30% density versus Intel 3, Fab 52 Arizona, Clearwater Forest Xeon 6+ up to 288 E-cores and 17% IPC, 1H 2026 server launch); Intel Foundry's 16 June 2026 VLSI release (18A-P risk production, +9% / −18% versus 18A, 50 nm CPP, 180/160 nm cells, PowerVia 11% routed area and 10× droop, ~30% frequency at ~0.5 V, CFET inverter at 45 nm pitch); Samsung Foundry Forum 2023 (SF2 versus SF3: +12% performance, +25% power efficiency, −5% area; mobile 2025 / HPC 2026 / auto 2027) and Foundry Forum 2024 (SF2Z BSPDN, mass production slated 2027). SRAM bitcell 0.0175 µm² / ~38 Mb/mm² is from TSMC's IEDM 2024 N2 device paper as reported in the device community; it is a conference disclosure, not a product datasheet. Unofficial yield percentages are omitted on purpose. Node names are treated as names.