For a decade, Intel's process roadmap was a list of delays. Intel 18A is the first node in that run to reach volume roughly on the timeline Intel promised, and it arrived with two firsts at once: a gate-all-around transistor Intel calls RibbonFET and a backside power network called PowerVia. Intel's own spec sheet claims up to 18% higher performance at iso power, 38% lower power at iso performance, and 30% better chip density than Intel 3.
That makes 18A the test case for whether a US company can still run a leading-edge logic fab and sell it to outsiders. This full guide checks the claims against what is public as of October 16, 2026: the transistor and power technology, the products built on it, Fab 52 output and yields, the 18A-P and 18A-PT variants, how 18A compares with TSMC N2 and A16, the 14A follow-on, and the honest limits.
If the physics is new to you, keep Inside Deep Tech's GAAFET and nanosheet transistors guide and backside power delivery guide open in other tabs. This piece assumes the basics and focuses on Intel's implementation.
Last updated: October 16, 2026.
Key Takeaways
- Intel 18A pairs RibbonFET gate-all-around transistors with PowerVia backside power, and claims 30% density gain over Intel 3.
- Panther Lake (Core Ultra Series 3) launched at CES 2026 in more than 200 PC designs, and Xeon 6+ brought 18A to servers with up to 288 E-cores.
- An analyst note puts 18A output near 30,000 wafers per month across Arizona and Oregon, with yields now described as stable.
- 18A-P entered risk production in Q2 2026 as the variant aimed at outside customers, and 14A targets risk production in 2027.
- Honest limit: Intel Foundry still lost $2.1 billion in Q2 2026, and no large external 18A customer has a product shipping in volume.
What Intel 18A actually is
Intel 18A is a logic process node. The name means 18 angstroms, or 1.8 nanometers, but like every modern node name it is a marketing label rather than a measured feature size. Intel positions it as the first 2-nanometer class node developed and manufactured in the United States.
The node bundles three technology changes that previous Intel nodes did not have together:
- RibbonFET, Intel's gate-all-around transistor, where the gate wraps fully around stacked silicon ribbons instead of three sides of a fin.
- PowerVia, Intel's backside power delivery, which moves the power wiring and bumps under the transistors and leaves the front side for signals.
- Omni MIM capacitors, on-die capacitors that Intel says improve power integrity and reduce voltage droop for bursty compute loads.
Intel also treats 18A as a platform, not a single recipe. The family includes 18A for Intel's first products, 18A-P for performance and power tuning aimed at external customers, and 18A-PT, a base-die variant for 3D stacking. Intel says the node is the foundation for at least three upcoming generations of client and server products.
Intel 18A family specs at a glance
| Variant | Role | Headline claim (Intel) | Status (Oct 2026) |
|---|---|---|---|
| Intel 18A | First RibbonFET + PowerVia node | Up to 18% perf at iso power, 38% lower power, 30% density vs Intel 3 | High-volume production in the US |
| Intel 18A-P | Tuned for external customers | Over 9% perf at iso power or over 18% lower power vs 18A | Risk production since Q2 2026 |
| Intel 18A-PT | Base die for 3D stacks | Up to 25% density, 35% lower power vs Intel 3-T | Offered for 3DIC designs |
| Intel 14A | Next node, second-gen backside power | Defect density outpacing 18A at the same stage | PDK 0.9 due October 2026 |
Source: Intel 18A process page, Intel Q2 2026 results and the Q2 2026 earnings call. All performance figures are Intel's own and come from its June 2025 VLSI paper and internal analysis.
RibbonFET: Intel's gate-all-around transistor
FinFETs, which Intel introduced in 2011, wrap the gate around three sides of a vertical fin. At very short gate lengths, the uncovered side leaks current. RibbonFET replaces the fin with a stack of horizontal silicon ribbons, and the gate surrounds each ribbon on all four sides.
Intel describes the result as precise electrostatic control that improves short-channel effects and supports scaling beyond FinFET. The practical knobs are ribbon width and threshold-voltage options, which let designers trade speed for leakage cell by cell. Intel also claims production silicon shows about 30% higher CPU frequency at roughly 0.5 V versus FinFET designs, which matters most for battery-powered and dense server parts that run at low voltage.
Samsung and TSMC use the same basic idea under different names. Inside Deep Tech's GAAFET and nanosheet guide compares the three implementations, and the CFET guide explains the stacked nFET-over-pFET structure that comes after.
PowerVia: why backside power is the bigger change
In a conventional chip, power and signal wires share the same front-side metal stack above the transistors. Power wires need to be thick and wide, so they crowd out signal routing and waste voltage as current travels down through a dozen or more thin layers.
PowerVia moves the coarse-pitch power metals and bumps to the back of the wafer and connects them through nano-scale through-silicon vias embedded in every standard cell. Intel claims PowerVia cuts worst-case dynamic voltage droop by as much as 10x and enables up to 11% block-level area compaction in routed designs.
This is where Intel has a real lead. Intel 18A is the first high-volume node with backside power. TSMC's first-generation N2 does not have it; TSMC adds its Super Power Rail with A16, which TSMC now expects to reach volume production in 2027. The trade-off is manufacturing complexity: the wafer has to be flipped, bonded to a carrier and thinned before the back-side layers are built, which adds steps and new failure modes. The full mechanics are in Inside Deep Tech's backside power delivery guide.
What ships on Intel 18A today
Two product families prove the node in volume, and both are Intel's own.
Panther Lake: Core Ultra Series 3
Intel launched Core Ultra Series 3 at CES on January 5, 2026, calling it the first compute platform built on Intel 18A, powering more than 200 PC designs, with systems available globally from January 27, 2026. The architecture briefing promised up to 16 P-cores and E-cores, up to 12 Xe GPU cores, more than 50% faster CPU and graphics performance than the previous generation, and up to 180 platform TOPS.
Panther Lake is a multi-chiplet design. The CPU compute tile is on 18A, and other tiles can come from other processes and other fabs. Counterpoint estimates that 70% to 75% of Intel's volumes are built in Intel fabs and 25% to 30% at TSMC and others, so 18A is the most important tile, not the whole chip.
Xeon 6+: Clearwater Forest
Xeon 6+ is Intel's first 18A data-center CPU. Intel's product page lists up to 288 E-cores and 576 MB of last-level cache on the top Xeon 6990E+ at 450 W, and Intel claims a 17% IPC uplift over the prior E-core generation. Intel's Q2 2026 report confirms Xeon 6+ launched as its first server-class product on Intel 18A.
Clearwater Forest is also a packaging showcase. Its 18A compute tiles sit on base dies using Foveros Direct copper-to-copper hybrid bonding, the technology covered in Inside Deep Tech's hybrid bonding guide. That means a Clearwater Forest yield problem can come from the node or from the stack, and Intel has to get both right.
| Product | Segment | 18A role | Launch | Key spec |
|---|---|---|---|---|
| Core Ultra Series 3 (Panther Lake) | Laptops, edge, robotics | CPU compute tile | CES, Jan 5, 2026 | Up to 180 platform TOPS |
| Xeon 6+ (Clearwater Forest) | Cloud, telecom, edge AI | 12 E-core compute tiles | Q2 2026 | Up to 288 E-cores, 576 MB cache |
| Wildcat Lake | Entry laptops | Compute die | Ramping in 2026 | Named as a lead 18A product on the Q2 call |
Source: Intel CES 2026 release, Panther Lake architecture release, Xeon 6+ product page and the Q2 2026 earnings call.
Fab 52, output, and yields
Intel developed and qualified 18A in Oregon and ramps it for volume at Fab 52 in Chandler, Arizona. Intel describes Fab 52 as its fifth high-volume fab at the Ocotillo campus and part of the $100 billion it is investing in US operations.
Yields were the story of 2025. In May 2026, CEO Lip-Bu Tan told CNBC the node was "not good" when he arrived and that he is now seeing the 7% or 8% monthly yield improvement that counts as best practice. By July, Intel said 18A output increased meaningfully and yields continued to track ahead of expectations.
Capacity numbers come from analysts, not Intel. A BlueFin Research Partners note reported by TechPowerUp says Fab 52 and the Oregon site together produce about 30,000 wafers per month on 18A, enough for Intel's internal demand but not for a large outside customer. Treat that figure as an estimate.
One more detail matters for lithography watchers. Intel's Q2 2026 report says it entered high-volume manufacturing for a subset of Panther Lake using ASML's EXE High NA EUV. That is the first public claim of High-NA tools in volume production, covered in Inside Deep Tech's High-NA EUV guide. TSMC, by contrast, has no plans to use High-NA EUV for any node through 2029.
Intel Foundry customers: who is actually on 18A
This is the weakest part of the 18A story. Microsoft was named as an 18A foundry customer in February 2024 for an undisclosed chip, and several companies have run test chips. But the products shipping on 18A in volume today are Intel's own.
Intel's plan for outsiders shifted to 18A-P, which keeps design compatibility with 18A while adding performance. Counterpoint reports Intel delivered the 18A-P 1.0 PDK late in 2025 and is engaging external customers on it. Tan told CNBC that Intel expects commitments from multiple foundry customers in the second half of 2026.
On October 15, 2026, Wccftech reported a KeyBanc note claiming Intel has won contracts from Broadcom, Google, Apple, AMD, Microsoft and NVIDIA, while others still evaluate 14A and 18A-P. Intel has not confirmed those names, and analyst channel checks on foundry deals are often early or partial. Inside Deep Tech's take: wait for Intel or the customer to say it.
The financials show why customers matter. In Q2 2026, Intel Foundry reported $5.8 billion of revenue, mostly from Intel's own products, and an operating loss of $2.1 billion. A foundry with one dominant customer that is also its parent is not yet a foundry business.
The US government is now a shareholder in that bet. Under the August 2025 agreement, the government invested $8.9 billion for a 9.9% stake, funded by CHIPS Act grants and the Secure Enclave program.
Intel 18A vs TSMC N2 vs TSMC A16
| Intel 18A | TSMC N2 | TSMC A16 | |
|---|---|---|---|
| Transistor | RibbonFET (GAA) | First-gen nanosheet (GAA) | Nanosheet (GAA) |
| Backside power | Yes, PowerVia | No | Yes, Super Power Rail |
| Volume production | High-volume in the US; Panther Lake from late 2025 | Started 4Q25 | Volume production expected in 2027 |
| External customers shipping | None confirmed in volume | Broad (TSMC's model) | Not yet in volume |
| Where made | Oregon and Arizona | Taiwan | Taiwan |
Source: Intel 18A page, Tom's Hardware on TSMC N2 volume production and TSMC's 2026 roadmap. Direct density and speed comparisons between Intel and TSMC nodes are not published on a common basis, so this table compares features and status, not PPA.
The honest read: Intel is first to backside power in volume, and TSMC is first to a broad gate-all-around customer base. For an AI chip designer, TSMC's ecosystem, packaging capacity and track record still dominate. Intel's pitch is US manufacturing plus backside power plus advanced packaging such as EMIB and Foveros, which some customers want as a second source.
What comes after 18A: 14A
Intel 14A is the node meant to win external customers at scale. On the Q2 2026 call, Tan said 14A defect density and transistor performance are outpacing 18A development, PDK 0.5 is complete and PDK 0.9 is on track for October. Intel committed to 14A risk production in 2027 and high-volume ramps in 2028.
14A is also where Intel plans its second generation of backside power and broader High-NA EUV use. Past 14A, the industry roadmap points to stacked transistors, covered in the CFET guide.
Inside Deep Tech's take
Inside Deep Tech's take: Intel 18A is a technical success that arrived late enough to make the business case harder. RibbonFET and PowerVia are in shipping laptops and servers, yields are reportedly at mature levels, and the node is the first to put backside power into volume.
But a foundry node is judged by other people's chips. Until a large external design ships on 18A or 18A-P, the node is best understood as Intel's internal process with a strong demo reel. The checkpoint that matters is the customer commitments Intel has promised for late 2026 and early 2027.
Honest limits
First, the performance claims are Intel's. The 18%, 38% and 30% figures compare 18A with Intel 3 using Intel's own analysis, not with TSMC N2, and no independent body publishes like-for-like node benchmarks.
Second, capacity is small. If the 30,000 wafers-per-month estimate is right, 18A has room for Intel's own products and little else until more capacity comes online.
Third, Panther Lake is not all 18A. Only the compute tile is, and a quarter or more of Intel's volume is still built outside Intel fabs.
Fourth, the foundry still loses money. An operating loss of $2.1 billion in Q2 2026 is an improvement, not a profit.
Fifth, customer names are unconfirmed. Reports of Apple, Google and NVIDIA wins come from analyst notes, not contracts that Intel or those customers have announced.
FAQ
What is Intel 18A?
Intel 18A is Intel's 2-nanometer class logic process. It combines RibbonFET gate-all-around transistors with PowerVia backside power delivery, and Intel claims up to 30% better density than Intel 3.
Which chips use Intel 18A?
Intel's own products: Core Ultra Series 3 (Panther Lake), Xeon 6+ (Clearwater Forest) and Wildcat Lake. No external customer has an 18A product shipping in volume as of October 2026.
Is Intel 18A better than TSMC 2nm?
It has one clear feature lead: backside power, which TSMC adds only with A16, now due in volume in 2027. TSMC N2 has the larger customer base and ecosystem. No public, like-for-like PPA comparison exists.
What is the difference between RibbonFET and PowerVia?
RibbonFET is the transistor: a gate wrapped around stacked ribbons. PowerVia is the wiring: power moved to the back of the wafer. Intel claims PowerVia cuts worst-case voltage droop by up to 10x. See the backside power guide.
What are Intel 18A yields in 2026?
Intel doesn't publish a yield number. Tan said in May 2026 that yields were improving 7% to 8% per month, and an analyst note says 18A has reached mature-node defect levels.
When is Intel 14A coming?
Intel targets 14A risk production in 2027 and high-volume ramps in 2028, with the PDK 0.9 release due in October 2026.
What to watch next
Three signals will tell you whether 18A becomes a foundry node. First, Intel's Q3 2026 results, due in late October, and whether they name 18A-P or 14A customers. Second, the 14A PDK 0.9 release this month. Third, a shipping external product on 18A or 18A-P, with its maker named on the record.
For the technology underneath, read Inside Deep Tech's backside power delivery guide, the GAAFET and nanosheet guide, the High-NA EUV guide and the hybrid bonding guide.
