EUV Lithography: A Full Guide to How ASML Machines Work and Why AI Chips Depend on Them

Extreme ultraviolet lithography is not a better lamp in a familiar projector. It is a vacuum machine that vaporizes tin 50,000 times a second, bounces 13.5-nanometer light off atomically smooth mirrors, and prints the most difficult layers of every leading-edge logic and DRAM chip that exists.

In 2026 that machine is no longer a science project. ASML is the only company that sells one. It expects to ship around 65 Low-NA EUV systems this year, has already recognized revenue on a High-NA tool, and on 15 July confirmed that Intel Foundry is using High-NA EUV in high-volume manufacturing on selected layers of Intel 18A. The reason accelerator lead times stay long is often not just HBM or packaging. It is also the scanner that has to print the silicon before anyone can stack it.

Key takeaways

• EUV is photolithography at 13.5 nm, more than 14 times shorter than 193 nm DUV. ASML's EUV systems are the only commercial tools that generate and use that light in a fab.
• The light is a tin plasma, not a laser shining through a lens. Molten tin droplets about 25 microns across are hit twice by a CO2 laser, 50,000 times a second. Because air and glass absorb EUV, the optical path is a vacuum full of multilayer mirrors, not lenses.
• Low-NA (0.33) is the 2026 workhorse. High-NA (0.55) is now a production option, not a slide. NXE tools resolve about 13 nm. EXE tools resolve about 8 nm. Intel is first to ship a high-volume logic product with High-NA layers; those layers are dual-qualified against the existing NXE fleet.
• Capacity, not physics, is the near-term constraint. ASML's 2026 Low-NA output is around 65 systems, with a planned 30% add in 2027 and a further 30% under study for 2028. 2027 Low-NA capacity is close to fully covered with orders.
• Only a handful of companies can buy one, and China cannot. TSMC, Samsung, Intel, SK hynix, and Micron are the relevant customers. Dutch and U.S. export rules keep EUV out of China. There is no second vendor.
• EUV does not print the whole chip. Most layers still use DUV. EUV is reserved for the densest, most overlay-critical layers. That is why DUV immersion still ships at around 130 systems a year alongside EUV.

EUV lithography at a glance

What EUV actually is

Start with the thing it is not. EUV will not appear in a smartphone the way a camera module does. It is not a process node. And "ASML" is not a synonym for "chips."

Photolithography is a projection system. Light carries a pattern from a mask (the reticle) onto a wafer coated with photoresist. Chemistry then turns that latent image into etched features. The industry has been doing this since the 1960s, walking the wavelength down from mercury lamps (436 nm, then 365 nm) through krypton-fluoride lasers (248 nm) to argon-fluoride lasers (193 nm). Each shorter wavelength printed smaller features. At 193 nm, even with immersion water between the lens and the wafer, the physics ran out of easy headroom.

EUV's answer is geometric in a different way. Drop the wavelength to 13.5 nm — close to soft X-ray — and the Rayleigh criterion, CD = k1 x lambda / NA, gives you a new floor. ASML's Low-NA tools run a numerical aperture of 0.33 and quote 13 nm resolution. High-NA tools raise NA to 0.55 and quote 8 nm. The price is that almost everything that used to be simple becomes hard. Glass absorbs the light. Air absorbs the light. The source has to be a plasma. The optics have to be mirrors. The reticle has to be reflective. The whole column has to sit in vacuum.

That is why only one company ships these machines, why they cost on the order of a mid-size office building, and why a leading-edge wafer still spends most of its lithography steps on older DUV tools. EUV is for the layers that 193 nm can no longer print in a tolerable number of exposures.

The problem EUV is solving

An AI accelerator is a lithography product wearing a software costume. The logic die, the I/O die, and the DRAM in every HBM stack are patterned, layer by layer, on 300 mm wafers. When those wafers cannot be printed, advanced packaging has nothing to assemble, and CoWoS slots sit empty.

The same constraint is why AI chip startups challenging NVIDIA so often discover that a clever datapath is not a product. Someone still has to buy a foundry wafer that an EUV scanner has already touched. The state of AI infrastructure in 2026 is a story about power, packaging, memory, and lithography together, not about GPU architecture in isolation.

How the machine works, layer by layer

A working EUV scanner is six problems stacked on top of each other.

The light source

There is no EUV lamp. ASML's laser-produced plasma source fires molten tin droplets about 25 microns in diameter at roughly 70 meters per second. A first, weaker CO2-laser pulse flattens each droplet into a pancake. A second, stronger pulse vaporizes it into a plasma that emits 13.5 nm light. The cycle repeats 50,000 times a second. ASML's own description is the one that matters; vendor-adjacent blogs that skip the pre-pulse are describing a different, less efficient source.

A collector mirror sits near the plasma and catches a usable fraction of that light. Collector lifetime is a materials problem: tin debris, hydrogen, and heat will ruin a multilayer coating that is only nanometers thick. Source power is the reason EUV took more than two decades and, by ASML's account, more than 6 billion euros of R&D plus the acquisition of Cymer. A dim source means a slow scanner. A slow scanner means a more expensive wafer.

The mirrors, not the lenses

Deep-ultraviolet tools focus with glass. EUV cannot. Almost every material, including air, absorbs 13.5 nm light, so the optical column is a set of multilayer mirrors in high vacuum. Each mirror is a stack of more than 100 alternating layers, typically molybdenum and silicon, engineered so that interference reflects a usable fraction of the beam. ZEISS has made ASML's optics since the late 1980s. The company describes the High-NA mirrors as polished to less than one atom of roughness: if a mirror were the size of Germany, the tallest "mountain" would be a millimeter.

Every bounce costs photons. That is why the column is short on surfaces, why the reticle is reflective rather than transmissive, and why pellicles — thin membranes that protect the mask from particles without eating the beam — were a gating item for High-NA.

The projection optics shrink the reticle pattern by four. The wafer never sees the mask at 1:1.

The reticle

A DUV mask is a quartz plate with a chrome pattern that light shines through. An EUV mask is a multilayer reflector with an absorber pattern on top. Defects on that mirror are printed defects. Mask inspection, blank quality, and pellicles are therefore part of the lithography bill of materials, not a downstream yield afterthought.

The vacuum and the stages

The entire light path, from plasma to wafer, sits in high vacuum. Robot arms move wafers in and out through an airlock with a positioning accuracy of 25 um and a surface-temperature uniformity of 2 millikelvin. Inside, a dual wafer stage — the TWINSCAN architecture — exposes one wafer while the other is aligned. ASML specifies the exposure stage to a quarter of a nanometer, checking and adjusting 20,000 times a second.

Overlay is the unglamorous number. A High-NA tool that prints 8 nm features is useless if layer N does not land on layer N-1. Intel and ASML quote 0.7 nm overlay on the EXE:5200B. That figure is a machine spec, not a process-of-record yield.

Resist, dose, and stochastic noise

Photons at 13.5 nm are expensive and few. Photoresist has to turn a sparse photon rain into a sharp chemical switch without line-edge roughness that eats the overlay budget. Higher source power, better resists, and computational lithography (inverse lithography, source-mask optimization) are how the industry keeps k1 from blowing up. This is also why "just buy High-NA" is not a complete process. The scanner is necessary. It is not sufficient.

The generations, compared

The headline change in High-NA is not a new wavelength. It is a fatter cone of the same 13.5 nm light. Raising NA from 0.33 to 0.55 is a 1.67x jump. ASML's resolution claim moves from 13 nm to 8 nm, about 1.6x, which is what the optics say you should get if k1 holds. Density is a layout question, not a poster. A 2.9x transistor-density claim is a theoretical ceiling for layers that actually use the extra resolution, not a chip-level multiplier.

Vendors then spend the extra NA in two ways. They print smaller features in one exposure, or they replace two or three Low-NA exposures with one High-NA exposure and buy back overlay and cycle time. Intel's 2026 insertion is the second kind of use: selected layers, dual-qualified, yields matched to NXE. That is a manufacturing option, not a node rename.

What actually shipped in 2026

This was the year High-NA left the R&D cleanroom and touched a product, while Low-NA remained the volume business.

Two caveats belong next to that table.

First, "first" is doing several jobs. Intel was first to install a commercial High-NA tool, first to accept an EXE:5200B, and first to ship a high-volume logic product with High-NA layers. Those claims can coexist with TSMC and Samsung remaining the largest Low-NA customers.

Second, dual-qualified is not the same as converted. ASML's 15 July 2026 High-NA release is explicit: specific 18A layers in Oregon, a subset of Core Ultra Series 3, yields matched to the NXE platform. Regular 18A production still runs on Low-NA. Anyone writing that "Panther Lake is a High-NA chip" is flattening a process option into a marketing slogan.

Who makes it, and who is allowed to buy it

The commercial EUV market is a one-firm industry. Nikon and Canon compete in DUV. They do not sell EUV. That concentration is not a temporary accident. The source, the mirrors, the vacuum stages, and the computational lithography stack took decades of joint work among ASML, ZEISS, Cymer, and a small set of customers who paid to be on the learning curve.

ASML

The only vendor. In Q2 2026 it reported 9.326 billion euros of sales and 2.918 billion euros of net income. The earnings release is the primary source for the capacity numbers that matter: around 65 Low-NA EUV systems in 2026, around 130 DUV immersion systems, a 30% Low-NA capacity add planned for 2027, and a further 30% under investigation for 2028. Full-year 2026 sales are now guided at 43 to 45 billion euros.

On the Q2 investor call, management put Q2 net system sales at 6.6 billion euros, of which 3.8 billion euros was EUV — including one High-NA system — and 2.8 billion euros was non-EUV, split 51% logic and 49% memory. Treat the one High-NA recognition as a data point, not as a run-rate. Installed-base service and upgrades were 2.8 billion euros in the quarter and are becoming a larger share of the story as the NXE fleet ages into a software-and-optics upgrade market.

List prices are not in the filings. Reported figures cluster around 150 to 200 million euros for a current Low-NA NXE tool and roughly double that — on the order of 350 to 400 million dollars — for a High-NA EXE. Use those as industry-reported bands, not as a quote you can send to procurement.

The customers

TSMC, Samsung Foundry, and Intel Foundry buy the logic tools. SK hynix, Samsung Memory, and Micron buy the DRAM tools. That is the 2026 list. A startup ASIC still meets EUV as a line item on a TSMC or Samsung process design kit, not as a purchase order to Veldhoven.

Memory is no longer a footnote. ASML's 2026 commentary puts memory system sales up on the order of 75% as DRAM makers raise lithography intensity for advanced nodes, including the DRAM that becomes HBM. An HBM cube is a packaging and stacking problem. The bits inside it are a lithography problem first.

Export controls

EUV scanners are subject to Dutch export licensing, aligned with U.S. semiconductor-equipment rules. ASML does not ship EUV to China. That is a legal fact, not a strategy slide. SMIC and Hua Hong compete at mature and some restricted advanced nodes with DUV multi-patterning. They are not in the 2026 EUV buyer set. DUV itself is separately licensed and is a different, leakier control surface.

Why the scanner, not just the wafer start, is the constraint

An EUV tool is a factory inside a factory. It ships in multiple loads, takes months to install and qualify, and then has to hit availability numbers that a 193 nm immersion tool would consider routine. Adding DRAM or logic wafer starts does not help if the critical-layer scanners are the limiting step.

That is the same shape of bottleneck we already documented on the back end: CoWoS-class packaging and HBM attach. Front-end EUV and back-end 2.5D are two scarce machines in series. A leading-edge AI die that cannot be printed cannot be packaged. A printed die that cannot be packaged is unfinished inventory.

It is also why foundry allocation is a procurement problem, not a design-win problem. Inference TCO comparisons that assume an unlimited supply of 3 nm or 2 nm wafers are doing hypothetical math. The real bill of materials includes an EUV slot, an HBM allocation, and a packaging slot in the same quarter.

What is real and what is hype

Real

• EUV is how every leading-edge logic chip and a growing share of DRAM is printed in 2026. There is no alternative commercial light source at 13.5 nm.
• Low-NA NXE is the volume platform. High-NA EXE has a production beachhead at Intel, on selected layers, with yields ASML says match NXE.
• ASML's 2026 Low-NA build of around 65 tools, with 2027 capacity close to fully ordered, is the capacity number that matters for AI wafer supply.
• Memory lithography intensity is rising with HBM and advanced DRAM. EUV is no longer a logic-only story.

Hype

• "High-NA ends multi-patterning." It can replace some multi-patterning on some layers. It does not delete DUV, and it does not print an entire 18A or 2 nm chip in one pass.
• "TSMC or Samsung will flip to High-NA next quarter." They have not announced a 2026 High-NA high-volume insertion comparable to Intel's dual-qualified 18A layers. Extending Low-NA plus multi-patterning is a rational cost and risk choice until High-NA throughput, pellicles, and mask infrastructure are boring.
• "A second EUV vendor is coming." Not with a high-volume 13.5 nm scanner in this decade's procurement window.
• "Any AI chip can just move to 2 nm." Without a foundry wafer that an NXE or EXE has already printed, and without the packaging and memory to go with it, you have a slide.

A realistic timeline

One useful heuristic: watch High-NA wafers per day and dual-qualification expansions, not press-release numerical apertures. The generation that prints in volume at matched yield is the generation that matters.

The bottom line

2026 is the year EUV stopped being explained as "the machine that saved Moore's Law" and became a procurement constraint with a High-NA footnote.

The physics is settled. 13.5 nm light, reflective optics, a tin plasma, and a vacuum stage are how you print the layers that 193 nm cannot. The industrial problem is building enough of those machines, inserting High-NA only where it beats another pass of Low-NA, and allocating the wafers to a buyer list that is shorter than the demand list.

For anyone making decisions today, the split is clean. If the question is how to buy AI compute this year, EUV capacity is already inside the foundry quote — you are buying someone else's scanner time. If the question is whether a new process node is real, ask how many critical layers are single-exposure EUV, whether High-NA is dual-qualified or merely installed, and who has a 2026-2027 NXE slot.

Frequently asked questions

What is EUV lithography?

Extreme ultraviolet lithography is a chipmaking step that prints circuit patterns onto a wafer using light at a 13.5 nm wavelength. The light comes from a tin plasma, is steered by multilayer mirrors in vacuum, and exposes photoresist through a reflective mask. It is the standard way to print the densest layers of leading-edge logic and DRAM.

How is EUV different from DUV?

DUV uses 193 nm or 248 nm laser light and glass lenses, often with water immersion. EUV uses 13.5 nm light, mirrors, and vacuum. DUV still prints most layers on an advanced chip because it is cheaper and good enough. EUV is reserved for the layers where DUV would need too many patterning passes, or cannot meet the pitch at all.

Who makes EUV machines?

ASML, only. ZEISS supplies the projection optics. The light source technology came in large part from Cymer, which ASML acquired. Nikon and Canon remain DUV competitors. They are not EUV competitors in 2026.

What is High-NA EUV?

A new optical column with numerical aperture 0.55 instead of 0.33, on ASML's EXE platform. The quoted resolution moves from about 13 nm to about 8 nm. The EXE:5200B is the high-volume tool. Intel is using it on selected Intel 18A layers of some Core Ultra Series 3 processors, dual-qualified against Low-NA, as of ASML's 15 July 2026 announcement.

Why are EUV machines so expensive and scarce?

Because the source, the mirrors, the vacuum stages, and the cleanliness requirements are unique, because only one company integrates them, and because each tool takes a long time to build, ship, and qualify. ASML's 2026 Low-NA output of around 65 systems is a factory number, not a pricing glitch. 2027 capacity is already close to fully ordered.

Does every AI chip need EUV?

Every leading-edge AI accelerator logic die does, and so does the advanced DRAM that becomes HBM. Older nodes used for some I/O, analog, or power-management die do not. "The model was trained on EUV silicon" is still not a useful spec. Ask for the node, the foundry, and whether the memory is HBM.

Can China build chips without EUV?

It can build many chips, including some 7 nm-class products, with DUV multi-patterning. That path costs extra exposures, extra overlay risk, and extra cycle time. It is not the same process window TSMC and Samsung use at 5 nm, 3 nm, and 2 nm. EUV scanners are not licensed for shipment to China.

Will High-NA replace Low-NA?

No. Low-NA remains the volume printer. High-NA is an option for the hardest layers and, if the economics work, a way to retire some multi-patterning. ASML will keep selling and upgrading NXE tools for years after EXE is qualified more broadly. The two platforms are a mix, the way EUV and DUV are a mix.

Methodology

This guide is based on primary company disclosures available as of 17 August 2026: ASML's EUV product pages (NXE at NA 0.33 / ~13 nm resolution; EXE at NA 0.55 / ~8 nm); ASML's lithography-principles note on the tin-droplet source (25 um droplets, 70 m/s, 50,000 Hz, dual CO2 pulse); ASML's 15 July 2026 High-NA production announcement (Intel 18A, subset of Core Ultra Series 3, dual-qualified layers, yields matched to NXE); and ASML's 15 July 2026 Q2 results (9.3 billion euros sales, 54.0% gross margin, ~65 Low-NA EUV and ~130 DUV immersion systems in 2026, +30% Low-NA capacity planned for 2027). Q2 system-sales split (3.8 billion euros EUV including one High-NA tool) is from ASML's investor-call remarks the same day. High-NA list prices and non-Intel insertion dates are labeled as industry-reported estimates, not as ASML or TSMC filings. Overlay and 175 wafers/hour figures for the EXE:5200B are company-stated machine specs, not independent yield audits.