Backside Power Delivery: A Full Guide to PowerVia, Super Power Rail, and Why 2nm Chips Flip the Wiring

Backside power delivery is not a transistor, not a foundry node, and it is not a synonym for GAAFET. It is a wiring decision: move the power grid to the back of the wafer so the front-side metal can carry signals. The product the customer buys is still a CPU or an accelerator. The thing that switched is which face of the die the current arrives on.

That switch exists because the alternative ran out of tracks. For fifty years, power and signals shared the same interconnect stack above the transistors. Power wants fat, low-resistance lines. Signals want density. At the pitches where a nanosheet gate sits — Intel's own 18A-P disclosure puts contacted poly pitch at 50 nm — those two jobs cannot share a metal stack without IR drop, routing congestion, and wasted cell area. Buried power rails, nano-scale through-silicon vias, and a backside metal grid are the foundry answer. Intel's production name is PowerVia. TSMC's is Super Power Rail. Samsung's is BSPDN on SF2Z.

What changed in 2026 is not that the idea was invented. imec published buried-rail and backside-via schemes years ago; Intel's Blue Sky Creek test chip was a 2023 VLSI paper. It is that one foundry now ships the architecture in a client CPU, a second has a named node that is process-ready with a Q4 2026 mass-production target, and a third still has it on a 2027 slide. The useful question is which of those is a bill of materials, which is a qualified flow waiting for a customer tape-out, and which is still a Foundry Forum diagram.

Key takeaways

• Backside power is a routing decision, not a transistor. GAAFET wraps the gate around a stacked nanosheet channel. BSPDN moves VDD and VSS to the wafer's back. You can ship one without the other: TSMC N2 is GAA with a front-side grid; Intel 18A is GAA plus PowerVia; Samsung SF2 is GAA, with BSPDN reserved for SF2Z.
• The stack has three pieces, and vendors do not implement them the same way. Buried power rails sit in the front-end. Nano-TSVs (or vertical backside contacts) punch through thinned silicon. A coarse backside metal grid, then bumps, brings current from the package. Intel PowerVia embeds nano-TSVs in every standard cell and relocates coarse-pitch metals and bumps to the back. TSMC Super Power Rail on A16 uses vertical backside contacts into the source/drain so the front-side gate, cell footprint, and NanoFlex width knobs do not have to be redrawn.
• Front-side power ran out of room at GAAFET pitches, not at a marketing node name. Contacted poly pitch has stalled near 45–50 nm. Standard cells are crowded. Dynamic voltage droop — the transistor not seeing the voltage the SPICE deck assumed — is the performance tax. Intel's 2023 PowerVia test on an Intel 4 E-core (Blue Sky Creek) showed >90% cell utilization, >30% platform voltage-droop improvement, and a 6% frequency benefit. VLSI 2026 restated the production stack as 11% routed-area reduction and 10× lower dynamic droop.
• Intel ships. TSMC is process-ready. Samsung is 2027 on the last primary slide. Panther Lake (Core Ultra Series 3) is an 18A client SoC with PowerVia in high-volume production at Fab 52 in Arizona. TSMC's HPC page says A16 with Super Power Rail is targeted to be production-ready in 2026, 8–10% speed or 15–20% power versus N2P, up to 1.10× chip density. Samsung's June 2024 Foundry Forum put SF2Z BSPDN mass production in 2027. Later 2026 roadmaps that omit the SF2Z name are not a kill notice; they are also not a SKU.
• Density, IR drop, and thermal are three different bills. Density is the front-side tracks you get back. IR drop is the resistance of the path from bump to transistor. Thermal is what happens when you thin the wafer, put metal on the back, and then push more current through a smaller cell. Intel's 2023 disclosure said PowerVia thermals were in line with the higher power densities expected from logic scaling; 18A-P at VLSI 2026 claimed 20–40% lower thermal resistivity as a follow-on materials-and-design number, not as a reason the first node was free.
• 2026 AI GPUs are still mostly FinFET plus HBM and CoWoS. PowerVia is in Intel CPUs. Super Power Rail is an A16 feature aimed at HPC, not a 2026 Blackwell-class bill of materials. Do not read a backside-power slide as a training-GPU node.

Backside power at a glance

What backside power actually is

Start with the thing it is not. It is not GAAFET. A nanosheet wrap is a device geometry. PowerVia is a metal-stack geometry. Intel combined them on 18A; TSMC did not combine them on N2. It is not EUV. EUV prints the patterns that make the vias and the cells; High-NA is a later overlay and pitch tool, not a requirement for first-generation BSPDN. It is not a chiplet or a CoWoS interposer. Those move power and signals between dies. Backside power moves power through one die, from the package bump to the transistor, without monopolizing the front.

A conventional CMOS die is a sandwich. Transistors sit near the front of a thick wafer. A dozen or more metal layers climb off those transistors toward the bumps. The lower metals (M0/M1 and friends) are dense and resistive. The upper metals are fat and used as a power grid, a clock mesh, and a place to escape signals to C4 bumps. Every milliamp to a standard cell travels down that stack, through vias that get narrower every node, and shares tracks with the wires that actually compute.

BSPDN flips the last part of that picture. After the front-end and the signal interconnect are built, the wafer is bonded to a carrier, flipped, and thinned. A power grid is built on the newly exposed back. Connections from that grid land on the transistors through one of three families of vertical links:

• Buried power rail plus nano-TSV. A rail is sunk into the front-end (often in shallow-trench isolation) so the cell's local VDD/VSS does not occupy the first signal metals. A nano-scale through-silicon via, formed after thinning, ties that rail — or the middle-of-line contact — to the backside grid. This is the scheme imec popularized and the one Intel's early PowerVia language sits closest to: nano-TSVs in the cell, coarse metals and bumps on the back.
• Direct backside contact to source/drain. Instead of landing on a buried rail, a vertical backside contact (TSMC's "VB" in 2026 trade descriptions of Super Power Rail) hits the epitaxial source/drain. The pitch argument is density: you do not spend front-side tracks or cell height on a rail. The process argument is harder: you have to form a contact from the back into a few-nanometer-class S/D without wrecking the nanosheet stack you just wrapped.
• Hybrid / "Power Boost" dual contact. Intel's 18A-P Power Boost option, disclosed at VLSI 2026, keeps a front-side contact and a backside contact on the same device. The claim is drive current and frequency at matched capacitance, not a new node. It is a reminder that "backside" does not have to mean "front-side contacts go away."

The bumps move with the grid. Intel's 18A page is explicit: PowerVia "relocates coarse pitch metals and bumps to the back side of the die." The package still delivers current. The C4 (or hybrid-bond) interface is just looking at the other face of the silicon. That is why 18A-PT exists as a base die with backside power, pass-through TSVs, and a hybrid-bond interface: the power architecture and the 3D stacking architecture are now the same conversation.

Why the front-side grid ran out of room

The congestion is not a slogan. It is three numbers that stopped moving together.

Pitch. Contacted poly pitch on Intel 18A-P is 50 nm. TSMC N2 and Samsung SF2 live in the same band. That is not a failure of "2 nm." It is the honest geometry after FinFET CPP stalled. At that pitch the first metal layers have no spare tracks. A power rail in the cell is a track you cannot use for a pin or a short route.

Utilization. Place-and-route wants 80%+ of the standard cells filled, because empty tracks are area you paid EUV to print and then left blank. Front-side power is why utilization tops out. Intel's Blue Sky Creek result — greater than 90% cell utilization over large areas of the die, on an Intel 4 FinFET test chip that already had PowerVia — is the public existence proof that the limiter was the grid, not the transistor.

IR drop and droop. Resistance from bump to device wastes voltage. At 0.6–0.7 V, tens of millivolts of IR drop is a frequency tax. Dynamic droop is worse: a clock-gated block wakes, the local grid sags, and the cycle that was timed at nominal VDD is now timed at VDD minus a spike. Intel's June 2023 PowerVia test disclosure put platform voltage-droop improvement at more than 30% and frequency benefit at 6% on that Intel 4 E-core, versus a similar design without PowerVia. The VLSI 2023 paper (Intel PowerVia Technology: Backside Power Delivery for High Density and High-Performance Computing, DOI 10.23919/VLSITechnologyandCir57934.2023.10185208) is the peer-reviewed version of the same silicon: >90% cell utilization, >30% droop, 6% frequency. Three years later, at VLSI 2026, Intel Fellow Eric Karl's invited talk restated the production GAA-plus-backside stack as 11% routed-area reduction and 10× lower dynamic voltage droop, which the company translates as up to 6% frequency or more than 15% dynamic power versus a comparable front-side interconnect. Manju Shamanna's companion silicon talk put ~30% frequency improvement at ~0.5 V on CPU cores built with GAA and backside power. Those are Intel measurements of Intel silicon. They are still the cleanest public accounting of why anyone flipped the wafer.

GAAFET made the problem sharper, which is why this guide sits next to that one rather than inside it. A nanosheet library wants tunable sheet width, extra Vt options, and inner-spacer/channel-release yield. It does not, by itself, create extra metal tracks. Putting PowerVia in a GAAFET subsection is the right cross-reference. It is the wrong place to park the process, the three foundry implementations, and the 2026-versus-slides clock.

Density, IR drop, thermal

Three benefits get sold as one. They do not pay on the same schedule.

Density. Move the rails and the fat metals off the front and the router gets tracks. Intel's 11% routed-area number is a block-level compaction claim on a comparable interconnect, not a 11% cheaper wafer. TSMC's A16 density claim versus N2P is "up to 1.10× chip density" — 8–10% — on the HPC page, bundled with the Super Power Rail pitch, not as a transistor shrink. Samsung's 2024 Korea Economic Daily remarks, citing foundry PDK VP Lee Sungjae, put a 17% chip-size reduction, 8% performance, and 15% power on BSPDN versus a traditional front-side PDN. That is an executive quote in trade press, not a numbered Samsung newsroom PPA table. Treat it as directionally consistent and less anchored than Intel's VLSI numbers or TSMC's own A16-versus-N2P list.

IR drop. A backside grid can be thicker. The path from bump to device can be shorter. Nano-TSVs in every cell are a lot of parallel vertical paths, which is how you get a 10× droop number rather than a 10% one. The cost is via resistance and via yield. Intel 18A-P's 10–30% via-resistance improvement (VLSI 2026) is a follow-on materials-and-geometry claim on a node that already had PowerVia; it is an admission that the first via was not the last word.

Thermal. Thinning a wafer to expose nano-TSVs removes silicon that used to spread heat. Backside metal puts a copper-ish heat spreader where that silicon was. Which effect wins is a design, not a slogan. Intel's 2023 newsroom piece said the test chip's thermal characteristics were "in line with higher power densities expected from logic scaling," and that engineers developed mitigation so thermals would not become a blocker. Debug was the other new problem: you can no longer assume front-side probing sees the power grid. 18A-P's 20–40% lower thermal resistivity is a later, specific claim — materials plus design — and it is attached to the performance follow-on, not to Blue Sky Creek. Anyone who tells you backside power "runs cooler" without saying at what current density, what backside metal stack, and what package lid is selling a slide.

Intel PowerVia: a 2023 test chip, a skipped 20A, a 2026 CPU

Intel de-risked the wiring before the transistor. That sentence is the whole 2023–2025 plot.

The June 2023 newsroom disclosure and the VLSI paper are the primary sources. PowerVia was built on a trial node using Intel 4 FinFET transistors, the nano-TSVs and front-end interconnect planned for 20A, and a full backside power network. The vehicle was Blue Sky Creek, an E-core of the class that went into Meteor Lake. The point of the trial node was to stop PowerVia and RibbonFET from being the same science project. The public KPIs: >90% cell utilization, >30% platform voltage-droop improvement, 6% frequency, thermals in line with the scaling envelope, "acceptable debug times as Intel 4." Intel 20A, the newsroom said then, would introduce PowerVia in the first half of 2024, with 18A following.

20A did not become a product node you can buy. RibbonFET and PowerVia shipped together on 18A. That is the slides-versus-ships fact that 2023 coverage still pollutes. The Intel 18A foundry page is the 2026 spec sheet: PowerVia reduces worst-case dynamic voltage droop by as much as 10× and enables up to 11% block-level area compaction in routed designs; 18A is in high-volume production in the United States. Those 10× / 11% figures are the same ones Eric Karl walked through at VLSI 2026. They are now a production-node claim, not a test-chip claim.

Panther Lake — Intel Core Ultra Series 3 — is the existence proof. The 9 October 2025 architecture reveal called it the first client SoC on 18A, with high-volume production at Fab 52 in Chandler, Arizona, and broad availability from January 2026. CES 2026 was the commercial debut. Xeon 6+ Clearwater Forest is the first 18A server CPU, on a first-half 2026 launch window, up to 288 E-cores. PowerVia is in those products because 18A is in those products. It is not in a 2026 NVIDIA GPU.

Two follow-ons matter, and they are easy to flatten.

18A-P. Risk production as of the 16 June 2026 VLSI release. Design-rule compatible with 18A (same 50 nm contacted poly pitch, same 180/160 nm cell heights), 9% higher performance at iso-power or 18% lower power at iso-performance. Power Boost is a dual-contact, low-resistance transistor option — front-side plus backside — for drive current. The thermal-resistivity and via-resistance ranges (20–40%, 10–30%) live here. Risk production is not a rack of 18A-P servers. It is the stage at which you run customer-like silicon before you promise a ramp.

18A-PT. The foundry page's 3DIC variant: "industry first base die with backside power delivery," pass-through TSVs, die-to-die TSVs, hybrid-bond interface, up to 25% higher density and 35% lower power versus Intel 3-T, up to 9× die-to-die bandwidth density. This is PowerVia meeting chiplets, not a second client CPU. Treat it as a base-die offering, not as Panther Lake in a trench coat.

What Intel has not done, as of 20 August 2026, is put PowerVia under a merchant AI GPU that competes with a CoWoS-packaged TSMC part, or publish a three-foundry bake-off on the same design. The 6–12 month "lead" over TSMC that analysts like to write is a calendar statement about 18A versus A16, not a measurement on a common die.

TSMC Super Power Rail: A16, not N2

TSMC split the risk the other way. N2 is first-generation nanosheet GAA, volume production since 4Q 2025, front-side power. N2P is the same design rules with a claimed 5% performance uplift and, on the HPC page, 18% speed or 36% power and 1.2× logic density versus N3E. The super-high-performance MIM capacitor in the front-side network is the conservative power-integrity upgrade. Super Power Rail is not on that node.

A16 is the backside node. TSMC's own one-line description: nanosheet transistors with an innovative backside power rail, improved logic density and performance. The HPC platform page is the numbered primary source:

• Super Power Rail optimizes power delivery by freeing front-side routing for signals, substantially reducing IR drop, and maintaining gate density and layout flexibility.
• Versus N2P: 8–10% speed improvement, 15–20% power reduction, up to 1.10× chip density.
• "Ideal for high-performance computing (HPC) with complex designs, targeting to be production ready in 2026."

That last clause is doing a lot of work. Production-ready in 2026 is not "your 2026 training GPU is on A16." TSMC's VLSI 2026 paper T1.5 (the abstract circulating at the June symposium) restated the same 8–10% / 15–20% / 8–10% density envelope and a Q4 2026 mass-production target. Kevin Zhang's 2026 North American Technology Symposium language — A16 ready in 2026, product volume expected in 2027 as a function of customers — is the honest overlay. Both can be true. A process can be qualified in one year and fill a fab the next. Treat Q4 2026 as a foundry-readiness date. Treat named A16 products as a 2027 question unless a customer has put a SKU on a slide you can cite.

The architectural claim TSMC wants you to remember is the direct backside contact. SPR is described as connecting the backside grid to source/drain through vertical backside contacts while leaving front-side gate structure, cell dimensions, and NanoFlex-style width flexibility in place. That is a DTCO statement: do not force the customer to throw away the N2 library because you flipped the wafer. Whether that contact is "more advanced" than Intel's nano-TSV-in-every-cell is a process-integration argument the two companies will not settle in a press release. What you can say from primary sources: they are not the same drawing, they are aimed at the same congestion, and only one of them is in a 2026 laptop.

A14, on the same TSMC HPC page, is a different bet — "full-node PPA through dimensional scaling," 15% speed or 30% power and >20% logic density versus N2, production on track for 2028, NanoFlex Pro. A12 is listed as a second-generation backside power-rail technology. Do not merge A16, A14, and A12 because they all have an A. SPR is the A16 headline. A14's headline is a shrink. A12 is a later backside generation on the logic menu, not a 2026 wafer.

N2, N2P, and N2X remain the 2026 GAA volume story at TSMC. If you need a nanosheet without a wafer flip, that is still the product. If you need the flip, you are waiting on A16 and on a customer who will spend a CoWoS-class package on it.

Samsung SF2Z: a 2024 name, a 2027 date

Samsung's primary source is the 13 June 2024 Foundry Forum. SF2Z "incorporates optimized backside power delivery network (BSPDN) technology, which places power rails on the backside of the wafer to eliminate bottlenecks between the power and signal lines." Versus SF2, the first-generation 2 nm node, BSPDN "enhances PPA" and "significantly reduces voltage drop (IR drop), enhancing the performance of HPC designs." Mass production "is slated for 2027."

That is the whole official paragraph. There is no Samsung-newsroom equivalent of Intel's 10× droop table or TSMC's 8–10% / 15–20% list. The 17% size / 8% performance / 15% power figures attached to Lee Sungjae in August 2024 Korean coverage are useful color. They are not the SFF release.

SF2 itself is GAA (MBCFET) without the flip — Samsung's second foundry generation of gate-all-around after 3 nm, with mobile first and HPC as the 2026 foundry-plan bucket. SF2Z is the backside variant of that family, aimed at HPC, on a 2027 clock. Some 2026 foundry-roadmap recaps note SF2Z missing from a later SAFE Forum slide in favor of SF2P+ language. Missing from a slide is not a cancellation 8-K. It is also not a reason to write "Samsung BSPDN is in production." The defensible 20 August 2026 statement is: Samsung has a named 2 nm-class backside node, last anchored in a 2024 Forum at 2027 mass production, and has not published a 2026 PowerVia-class product.

Samsung was first to put GAA into a fab. It is not first to put backside power into a product. Those two sentences can live together. They usually do not, in vendor copy.

Three implementations, one congestion problem

A short mapping, because the slides will not provide one.

What still breaks

PowerVia is in production at Intel. That does not make nano-TSVs boring.

Thinning and handle-wafer flow. Bond, flip, thin, de-bond. Every one of those steps is a yield term that FinFET front-side power never paid. Edge exclusion, remaining silicon thickness uniformity, and carrier-wafer contamination are the unglamorous reasons TSMC did not put SPR on the first N2 mobile wave.

Vertical-link yield. A nano-TSV or backside S/D contact in every cell is a lot of holes. Opens are IR drop. Leakage is a dead cell. Intel's 2023 paper spent pages on reliability and fault isolation for a reason: you have to debug a grid you can no longer see from the front.

Design-technology co-optimization. Libraries, filler cells, decap, and ESD change when VDD does not arrive from M1. TSMC's "maintaining gate density and layout flexibility" line is a promise that A16 does not orphan N2 IP. Intel 18A-P being design-rule compatible with 18A is the same promise one node later. Someone still has to re-characterize the library.

HPC die size. A laptop tile is not a reticle-class accelerator. Backside power's IR-drop win is more valuable on a large, hungry die — which is why TSMC aimed A16 at HPC and Samsung aimed SF2Z at HPC — and the yield tax is also higher there. The first product on a new PDN is rarely the biggest die the foundry will ever run.

Package interaction. BSPDN changes which face the bumps sit on and how current spreads before it hits a CoWoS interposer or an EMIB bridge. It does not replace the interposer, the HBM PHY, or the organic (or glass) substrate. Confusing wafer-level PDN with package-level PDN is how you get a slide that says "backside power solves AI power."

A realistic timeline

One useful heuristic: ask whether the node in the product actually has the backside grid, whether the vertical link is a nano-TSV or a direct S/D contact, and whether the die is a CPU tile or a reticle-class accelerator. Do not ask whether the foundry "supports backside power."

The bottom line

2026 is the year backside power delivery stopped being a VLSI test chip and became a laptop — and the year it still did not become a GPU.

The physics is old. At 50 nm-class contacted poly pitch, power and signals cannot share a front-side stack without giving up utilization, voltage, or both. Buried rails, nano-TSVs, and a backside metal grid are how you stop paying that tax. Intel de-risked the grid on FinFET, skipped 20A as a product, and shipped PowerVia with RibbonFET on 18A. TSMC shipped the nanosheet first and parked Super Power Rail on A16, which it says will be production-ready in 2026 for HPC. Samsung wrote SF2Z in 2024 and dated it 2027. Those are three defensible risk orders. They are not three 2026 products.

For anyone making decisions today, the split is clean. If the question is what is inside a Panther Lake laptop or a Clearwater Forest Xeon, you are looking at GAAFET and PowerVia. If the question is what is inside a 2026 flagship phone on N2, you are looking at GAAFET and a front-side grid. If the question is what is inside a 2026 training GPU, you are still looking at FinFET logic, HBM, and CoWoS — with A16 Super Power Rail in the foundry queue behind them, not under them. If the question is whether a vendor's "backside power" story is real, ask which node, which vertical link, which numbered droop or density claim, and the name of the product that already came off that line. The angstrom in the node name will not answer it.

Frequently asked questions

What is backside power delivery?

A wafer-level architecture that puts the chip's power grid on the back of the die — after thinning — and connects it to the transistors with nano-TSVs or backside source/drain contacts. Front-side metals then carry signals. It is also called BSPDN (backside power delivery network).

How is PowerVia different from Super Power Rail?

Both move power to the back. Intel PowerVia, on 18A, embeds nano-TSVs in every standard cell and relocates coarse-pitch metals and bumps to the back. TSMC Super Power Rail, on A16, is described as using vertical backside contacts into the source/drain while keeping front-side gate density and NanoFlex-style layout flexibility. They are competing implementations, not two names for one process.

Is backside power the same as GAAFET?

No. GAAFET is the transistor (a gate wrapped around stacked nanosheets). Backside power is the metal stack that feeds it. Intel 18A has both. TSMC N2 has GAAFET only. See our GAAFET guide for the device; this guide is the wiring.

Why did front-side power run out of room?

At ~50 nm contacted poly pitch, standard cells have no spare tracks. Power rails steal routing, via resistance eats voltage, and dynamic droop shows up as frequency you cannot keep. Utilization stalls below what the router could fill if the grid were somewhere else.

Does TSMC N2 use backside power?

No. N2 and N2P are front-side-powered nanosheet nodes. Super Power Rail arrives on A16, which TSMC says is targeted to be production-ready in 2026, with product volume commonly discussed as 2027.

Is Intel 18A in production with PowerVia?

Yes. Intel's 18A page states high-volume production in the United States. Panther Lake (Core Ultra Series 3) is the first client product; Xeon 6+ Clearwater Forest is the first server product in the 1H 2026 window. 20A, the 2023 slide that was supposed to introduce PowerVia in 2024, is not the product node.

When will Samsung ship BSPDN?

Samsung's June 2024 Foundry Forum slated SF2Z mass production for 2027. SF2, the first 2 nm-class MBCFET node, does not include it. There is no 2026 Samsung product you can point at as a PowerVia equivalent.

Will backside power show up in 2026 AI GPUs?

Not as the volume path. 2026 training accelerators remain FinFET logic with HBM on CoWoS. A16 is the TSMC node that adds Super Power Rail for HPC; readiness in 2026 is not the same as a named GPU SKU. Intel's PowerVia volume is CPUs.

Does backside power replace CoWoS, HBM, or EUV?

No. EUV still prints the patterns. HBM is still the on-package memory. CoWoS (or EMIB, or another 2.5D/3D flow) still joins the dies. Backside power only changes how current crosses one piece of silicon. Chiplets still partition the product.

Is backside power a thermal win?

It can be, if the backside metal spreads heat better than the silicon you thinned away. It can also concentrate heat in a thinner die. Intel's 2023 test said thermals were in line with expected scaling; 18A-P later claimed 20–40% lower thermal resistivity. Neither number is a guarantee on an arbitrary HPC die.

Methodology

This guide is based on primary foundry and device disclosures available as of 20 August 2026: Intel's 5 June 2023 newsroom piece "PowerVia Test Shows Industry-Leading Performance" (Blue Sky Creek on an Intel 4 trial node, >90% standard-cell utilization, >30% platform voltage-droop improvement, 6% frequency benefit, thermals in line with scaled power density, PowerVia then planned for Intel 20A in 1H 2024) and the companion VLSI 2023 paper Intel PowerVia Technology: Backside Power Delivery for High Density and High-Performance Computing (DOI 10.23919/VLSITechnologyandCir57934.2023.10185208); Intel Foundry's 18A process page (PowerVia 10× worst-case dynamic droop and up to 11% routed-area compaction, 18A in high-volume U.S. production, 18A-P and 18A-PT follow-ons); Intel Foundry's 16 June 2026 VLSI Symposium release (18A-P risk production, +9% / −18% versus 18A, 50 nm CPP, 180/160 nm cells, Power Boost dual contact, 20–40% thermal resistivity, 10–30% via resistance, Eric Karl 11% area and 10× droop, Shamanna ~30% frequency at ~0.5 V); Intel's 9 October 2025 Panther Lake architecture announcement (first 18A client SoC, Fab 52 Arizona, Clearwater Forest Xeon 6+ 1H 2026). TSMC's A16 technology page and HPC platform "Advanced Technologies" page (A16 = nanosheet + Super Power Rail, 8–10% speed / 15–20% power / up to 1.10× chip density versus N2P, production-ready in 2026, N2 volume from 2025, N2P design-rule compatible); TSMC VLSI 2026 paper T1.5 abstract as reported at the June symposium (same PPA envelope, Q4 2026 mass-production target). Samsung Foundry Forum 13 June 2024 newsroom release (SF2Z BSPDN, power rails on the wafer back, PPA and IR-drop language versus SF2, mass production slated for 2027). Lee Sungjae's 17% / 8% / 15% remarks are Korea Economic Daily / TrendForce 2024 reporting, not the SFF release, and are labeled as such. Intel 20A is treated as a skipped product node: the 2023 plan of record, not a 2026 SKU. Unofficial yield percentages and unsourced "6–12 month lead" scorecards are omitted or labeled as analysis. GAAFET device physics, N2/18A/SF2 transistor PPA, and SRAM bitcells are covered in our GAAFET guide and are not re-derived here except where they intersect the power grid.