TSMC CoWoS: A Full Guide to the Packaging Line That Gates AI GPUs

CoWoS is not a transistor. It is not a foundry node, and it is not a synonym for "advanced packaging." It is TSMC's Chip-on-Wafer-on-Substrate product family: a 2.5D assembly flow that sits logic dies and HBM stacks on an interposer, then lands that sandwich on an organic substrate. The product the customer buys — an NVIDIA GPU, an AMD Instinct accelerator, a Broadcom-built TPU or custom XPU — is the package. The silicon inside it is a kit that only becomes a product after it leaves the CoWoS line.

That kit exists because the alternative ran out of area. A leading-edge scanner field is about 26 mm by 33 mm, roughly 858 mm². EUV lithography prints the transistors; it does not enlarge the field. NVIDIA's Hopper H100 was already living at that edge as a single die. Blackwell and Blackwell Ultra are two reticle-sized dies, 208 billion transistors, stitched into one GPU and sat next to eight HBM stacks. You cannot ship that object off a standard organic substrate. You need a dense, millimeter-scale interconnect under the dies. At TSMC, that interconnect is CoWoS.

What changed in 2026 is not that CoWoS arrived. TSMC has been in volume on the platform since 2012, when Xilinx FPGAs were the first customer. It is that the company is now producing 5.5-reticle CoWoS, has a public 14-reticle roadmap for 2028, and that its own chairman said on the 16 July 2026 earnings call that packaging capacity is so tight it now limits customer growth. The useful question is which CoWoS variant a given AI package actually uses, why silicon interposers stopped scaling, and why a company can have ample N4 or N3 wafers and still miss a quarter because it did not get a CoWoS slot.

Key takeaways

• CoWoS is TSMC's 2.5D assembly product, not a process node. Chip-on-Wafer bonds logic and HBM to an interposer. Wafer-on-Substrate attaches that assembly to an organic package. GAAFET and EUV decide how small the transistors are. CoWoS decides whether those transistors become a GPU.
• Three variants, three interconnects. CoWoS-S is a full silicon interposer with through-silicon vias, up to 3.3× reticle (~2,700 mm²). CoWoS-R replaces that silicon with a polymer/copper redistribution-layer (RDL) interposer, in volume since 2023. CoWoS-L embeds local silicon interconnect (LSI) bridges in an RDL interposer so the package can grow past the silicon-interposer ceiling. TSMC's first 3.5× CoWoS-L has been in volume since 2024; 5.5× is in production in 2026.
• The bottleneck is the assembly slot, not the transistor. Chairman and CEO C.C. Wei said on the Q2 2026 call that packaging capacity "is so tight that now it limits my customers' growth." HPC — the bucket that includes AI accelerators — was 66% of TSMC's Q2 2026 revenue. A logic wafer that cannot be packaged is not an accelerator.
• NVIDIA, AMD, and Broadcom are competing for the same line. Blackwell-class GPUs, AMD Instinct, Google TPUs, AWS Trainium, and merchant XPUs all need large CoWoS (or a close cousin). Allocation is a purchase-order fight, not a technology debate. Analyst estimates that NVIDIA takes on the order of 60% of CoWoS demand are widely cited and not a TSMC disclosure; treat them as analysis.
• HBM lives on CoWoS. SoIC can feed it. HBM stacks sit a few millimeters from the GPU on the same interposer. TSMC-SoIC is a separate, front-end 3D hybrid-bond stack that can then be dropped into CoWoS or InFO as if it were one die. Confusing the two produces vendor copy. Chiplets and UCIe are the architecture and the protocol. CoWoS is how TSMC joins the dies.
• Bigger than 3.3× reticle is a different product. TSMC's own page recommends CoWoS-L or CoWoS-R once the interposer exceeds 3.3×. The 14-reticle CoWoS slated for 2028 — about 10 large compute dies and 20 HBM stacks — is a CoWoS-L-class object, not a giant piece of silicon interposer. System-on-Wafer (SoW-X) at 40 reticles in 2029 is a later, still-roadmap envelope.

CoWoS at a glance

What CoWoS actually is

Start with the thing it is not. It is not advanced packaging as a category — that survey covers EMIB, Foveros, fan-out, and hybrid bonding as a landscape. CoWoS is one foundry's named 2.5D product family. It is not a chiplet architecture. Chiplets are how you partition a SoC. CoWoS is how TSMC puts those partitions, plus memory, onto one substrate. And "we use CoWoS" on a slide does not tell you whether the interposer is a slab of silicon, an RDL film, or silicon bridges in a mold.

The name is the process, in order.

Chip-on-Wafer (CoW). Known-good logic dies and HBM cubes are flipped onto a reconstructed wafer that will become the interposer. Microbumps make the joints. This is the yield-critical, foundry-like step: alignment, underfill, warpage, known-good-die handling. TSMC has historically kept CoW in-house. OSAT partners (ASE, Amkor, SPIL) have long taken overflow on the next step; 2026 reporting says some CoW front-end work is being farmed out as well. That last claim is supply-chain reporting, not a TSMC 8-K. Treat it as analysis.

Wafer-on-Substrate (WoS). The populated interposer is diced and attached to a conventional organic package substrate with C4 bumps. Power, SerDes, and board I/O leave through that substrate. The object that ships to the board house is a BGA, not a wafer.

The reason this exists is geometric. A 193 nm scanner field of ~858 mm² is the largest rectangle a logic die can be if you want one continuous design. Interposers can be stitched across multiple fields. HBM PHYs, GPU SM arrays, and 112G SerDes do not want the same process node anyway. Put the dies on a dense interposer and you beat the reticle, mix nodes, and keep the HBM a few millimeters from the compute rather than centimeters down a board.

TSMC's CoWoS technology page is the primary source for the family split. CoWoS-S takes a silicon interposer to 3.3× reticle, about 2,700 mm². For anything larger, the page's own language is to use CoWoS-L or CoWoS-R.

How the three variants actually differ

Vendor copy flattens "CoWoS" into one product. It is three interconnect strategies sharing a brand.

CoWoS-S: the silicon interposer

CoWoS-S is the original. A full silicon interposer, through-silicon vias, high-density interconnect, and embedded deep-trench capacitors (eDTC) under the logic. Production since 2012. The silicon gives you the finest wiring, the best-integrated decoupling, and a mature yield story. It also gives you a wafer of expensive, TSV-bearing silicon whose area is the product.

TSMC's published ceiling is 3.3× reticle, ~2,700 mm². An IEEE ECTC 2021 paper on fifth-generation CoWoS-S described a high-performance silicon interposer at 2,500 mm² — already in the multi-reticle class. That is a conference disclosure of a generation, not a 2026 SKU datasheet, but it is the right scale: thousands of square millimeters of silicon whose only job is to be wiring.

Hopper-class NVIDIA GPUs and a long list of HPC ASICs shipped on CoWoS-S. It is still the right answer when the package fits and you want maximum wiring density plus on-interposer capacitance. It is the wrong answer when you need 5.5× reticle of real estate. You cannot grow a monolithic silicon interposer forever without stitching, yield loss, and a bill for TSVs across an area the size of a postage stamp.

CoWoS-R: the RDL interposer

CoWoS-R deletes most of that silicon. The interposer is a redistribution layer: polymer dielectrics and copper traces. TSMC says volume production started in 2023. Published features from the same CoWoS page:

• Minimum 4 µm pitch — 2 µm line width and spacing.
• Co-planar GSGSG routing and interlayer ground shielding for signal and power integrity, with a lower-RC line than a fat silicon stack.
• The RDL and C4/underfill stack as a CTE (coefficient of thermal expansion) buffer between the SoC and the organic substrate, cutting strain energy density in the C4 area.

The RDL interposer is relatively flexible. That is the mechanical point. A large silicon interposer on an organic substrate is a CTE fight; polymer and copper give you compliance. The electrical trade is density. 2 µm lines are not the sub-micron copper of a silicon interposer or an LSI bridge. CoWoS-R is the cost-and-scale option for packages that need more area than CoWoS-S wants to grow, without paying for silicon everywhere. AWS Trainium-class parts are widely reported on CoWoS-R. That customer mapping is industry reporting, not a TSMC product catalog.

CoWoS-L: RDL plus local silicon interconnect

CoWoS-L is the variant that now carries the largest AI packages. It keeps an RDL-based, molding-based interposer for area and mechanics, and inserts local silicon interconnect (LSI) chips — silicon bridges — only where you need silicon-density wiring. TSMC's page: LSI provides high-routing-density die-to-die interconnect through multiple layers of sub-micron copper; the metal types, layer counts, and pitches align with CoWoS-S; LSI can be reused across SoC-to-SoC, SoC-to-chiplet, and SoC-to-HBM links; stand-alone eDTCs can sit under the SoC for power integrity.

This is the same idea as Intel's EMIB (embedded multi-die interconnect bridge), executed as a TSMC wafer-level product with an RDL interposer around the bridges rather than bridges dropped into a conventional organic substrate. The distinction matters for who can build it and how large the reconstructed wafer can be. It does not mean CoWoS-L "is EMIB."

TSMC's first CoWoS-L at 3.5× reticle entered volume production in 2024. The 2026 North America Technology Symposium (22 April 2026) is the current size roadmap from the company itself: TSMC is now producing 5.5-reticle CoWoS; a 14-reticle CoWoS, "capable of integrating approximately 10 large compute dies and 20 HBM stacks," is slated for production in 2028; an expansion beyond 14 reticles follows in 2029, alongside 40-reticle SoW-X System-on-Wafer. TSMC's own HPC platform language says quality-and-reliability certified 5.5× mask/reticle interposers in 2025 and started volume in 2026. That is the production fact. 9.5× and 14× are roadmap.

NVIDIA's Blackwell generation is the public proof that CoWoS-L is load-bearing. The Blackwell architecture page states that Blackwell GPUs pack 208 billion transistors on a custom TSMC 4NP process, with two reticle-limited dies connected by a 10 TB/s chip-to-chip interconnect, behaving as one GPU. Independent package analyses (TechInsights, March 2025) identified the B200/GB100 as CoWoS-L rather than a monolithic silicon interposer — NVIDIA's first use of the bridge-based variant. Blackwell Ultra, per NVIDIA's technical blog, keeps the dual-die, 208-billion-transistor compute and raises on-package memory to 288 GB of HBM3e in eight 12-Hi stacks at 8 TB/s. That memory sits on the CoWoS package. It is not a board DIMM.

One useful heuristic: ask what the interposer is made of, not whether the slide says CoWoS. Silicon everywhere is -S. RDL everywhere is -R. Silicon only where the dies talk is -L.

Why this is the assembly bottleneck, not the node

A GAAFET on N2 or Intel 18A is a transistor. An EUV scanner is a patterning tool. Neither attaches eight HBM stacks to two reticle-sized GPUs. The 2026 volume AI accelerator is still mostly FinFET logic plus HBM plus a 2.5D package. The package is the long pole.

C.C. Wei said it in public on 16 July 2026, answering a question about competing advanced-packaging supply: "our packaging capacity is so tight that now it limits my customers' growth." He added that TSMC welcomes additional flexibility in the market because it helps TSMC's front-end wafer business — the majority of revenue — which is exactly the tell. Logic wafers are piling up behind the back-end. On the same call he said the majority of advanced packaging is still CoWoS; glass-core / glass-substrate work is a cost-down alternative on a pilot line that needs about another year to mature before production with a customer. About 10–20% of 2026 capex is budgeted for advanced packaging, testing, mask making, and others, against 70–80% for advanced process technologies. HPC was 66% of Q2 revenue.

That is the primary-source picture. Absolute wafers-per-month are not in TSMC's earnings release. Sell-side and trade-press estimates for end-2026 CoWoS capacity cluster around 120,000–140,000 wafers per month at TSMC, against demand talked about near a million wafers for the year, with NVIDIA commonly estimated near 60% of that demand and Broadcom plus AMD as the next two. Those figures move from note to note and should be read as analysis, not as a foundry datasheet. What does not move is the qualitative fact: the line is tight, the customers are the same three or four names, and a CoWoS-L package for a dual-die GPU plus eight HBM stacks consumes far more interposer area — hence more of a 300 mm reconstructed wafer — than a CoWoS-S H100-class part.

Capacity expansion is a real-estate story. TSMC is building, in Wei's Q2 2026 words, 13 leading-edge and advanced-packaging fabs in Taiwan over the next several years, plus additional Arizona investment that explicitly includes advanced-packaging fabs on top of 2 nm-capable logic. Taiwan's National Science and Technology Council said at a 12 July 2026 Chiayi Science Park Phase II groundbreaking that two advanced-packaging facilities in Phase I began mass production in June 2026, and that TSMC will add three more in a roughly 90-hectare Phase II. Industry naming for the existing back-end sites runs AP5/AP6 (Taichung/Zhunan), AP7 (Chiayi), and AP8 (Tainan, on a former Innolux site). TSMC does not publish a tidy AP-site capacity table; Chiayi mass-production in June 2026 is a government statement, Tainan/AP8 as a large CoWoS shell is widely reported. The operational point is the same: CoWoS is being cloned across southern Taiwan because one campus cannot print enough interposers.

AI chip startups chasing NVIDIA usually discover this before they discover a compiler bug. An N4/N3 allocation without a CoWoS slot and an HBM contract is a wafer, not a product. The same is true, in a milder form, for Broadcom-built custom silicon: the XPU is only as real as the packaging queue behind it.

CoWoS, HBM, and SoIC are three different objects

They get stacked in the same sentence because they get stacked in the same package. They are not interchangeable.

HBM is the memory chiplet. A stack of DRAM dies on a logic base die, sitting on the CoWoS interposer next to the GPU, talking JEDEC HBM2E/HBM3/HBM3e/HBM4 over a very wide, very short interface. Our HBM guide covers the stacks, the three suppliers, and the memory-side bottleneck. CoWoS is the board those stacks sit on. More HBM stacks (8, then 12, then the 20 on the 14-reticle 2028 sketch) is a CoWoS-area problem as much as an SK Hynix/Samsung/Micron output problem. You cannot place twelve HBM4 cubes around two compute dies on a 3.3× silicon interposer. That is why CoWoS-L exists.

SoIC is 3D stacking, not 2.5D. TSMC-SoIC is a front-end, hybrid-bonded chip-on-wafer or wafer-on-wafer stack with bond pitch starting from the sub-10 µm rule. TSMC's SoIC page is explicit: a SoIC assembly can subsequently go into CoWoS or InFO or SoW; 3 nm chip stacking entered volume in 2025; from the outside the stacked object looks like one SoC. The 2026 symposium puts A14-to-A14 SoIC in production in 2029 at 1.8× die-to-die I/O density versus N2-on-N2 SoIC. SoIC is how you put cache or logic on top of logic. CoWoS is how you put that stack next to HBM and a second compute die. AMD's MI300-class parts are the canonical SoIC-plus-CoWoS product: 3D stacked compute/I/O, then 2.5D with HBM.

Chiplets and UCIe are the split and the language. A dual-reticle GPU is a homogeneous chiplet partition. UCIe is the open die-to-die protocol. NVIDIA still uses NV-HBI for the 10 TB/s Blackwell link. AMD still uses Infinity Fabric. CoWoS-L's LSI is happy to carry any of those. The package does not care about the protocol until the PHY and the bump map do.

Co-packaged optics can sit on the same substrate. TSMC's COUPE optical engine is specified to land on CoWoS-based CPO in 2026. That is a switch-and-later-XPU story, covered in the CPO guide. It is not how 2026 training GPUs leave the package. Those still leave over copper and HBM.

Thermal is a package problem that becomes a facility problem. A 1,000–1,400 W dual-die GPU is why liquid cooling moved from optional to default in AI halls. CoWoS puts the heat sources a few millimeters apart on a shared interposer. Cold plates sit on the package lid. The packaging line does not solve the rack CDU. It creates the heat density that the CDU has to eat.

CoWoS versus EMIB, InFO, and "just use an OSAT"

The competitive set is real. It is also not a drop-in.

Intel EMIB / EMIB-T. Silicon bridges embedded in an organic substrate. No full interposer wafer, so the package can be rectangular and, in Intel's telling, large without reconstructing a 300 mm RDL wafer. Ponte Vecchio shipped on EMIB. It is the technically closest cousin to CoWoS-L, and on the Q2 2026 call an analyst asked Wei about EMIB-T "gaining traction." Wei's answer was the tightness quote: TSMC's packaging limits its customers, and more non-TSMC packaging in the market would help TSMC sell more front-end wafers. That is not a concession that EMIB replaces CoWoS on NVIDIA's bill of materials. NVIDIA's 2026 flagship GPUs are still a TSMC 4NP + CoWoS object.

TSMC InFO. Integrated fan-out: RDL in a reconstituted wafer, no silicon interposer. High-volume in mobile (InFO-PoP). InFO-oS is the HPC-leaning cousin for logic-to-logic. It is not how you attach eight HBM stacks at GPU shoreline density.

Samsung I-Cube / H-Cube, ASE FoCoS. Foundry and OSAT 2.5D alternatives. Relevant for non-NVIDIA ASICs that will not wait in TSMC's queue, or that tape out on Samsung. They do not currently absorb Blackwell-class dual-reticle plus eight-HBM packages.

Panel-level and glass-core. TSMC's own language on the Q2 2026 call: CoWoS is still the majority; glass is a cost-down alternative on a pilot line, about a year from customer production. Panel-level (CoPoS, chip-on-panel-on-substrate) is a later way to escape the round 300 mm wafer when 14-reticle packages start looking like substrates, not interposers. Roadmap, not 2026 BOM.

If the question is "can I get an AI accelerator without CoWoS in 2026," the honest answer is: yes, if you are not trying to be NVIDIA, and if you will accept EMIB, a smaller RDL, or fewer HBM stacks. If the question is "can I get a Blackwell-class GPU without a TSMC CoWoS slot," the answer is no.

Who is fighting for the slots

TSMC does not publish a customer-by-customer CoWoS table. The demand map is still legible.

NVIDIA is the anchor tenant. Every Hopper, Blackwell, and Blackwell Ultra GPU that needs HBM goes through this line. Dual-die CoWoS-L packages consume more area per unit than Hopper CoWoS-S, so a "unit of CoWoS" is not a GPU. Allocation through 2026–2027 is the constraint on how many GB200/GB300 NVL72 racks the world can actually stand up, which is why packaging news moves NVIDIA's quarter as much as N4 wafer starts do.

AMD needs CoWoS (often with SoIC in the stack) for Instinct. MI300-class and the MI400 generation are multi-die, HBM-heavy parts. AMD has also been the customer most visibly pushing OSAT CoW capability so the entire flow is not a single-foundry queue.

Broadcom is the merchant XPU vehicle: Google TPU and other hyperscaler custom dies, packaged at TSMC. In unit terms Broadcom can rival or exceed AMD's CoWoS draw in some sell-side maps; in product terms it is many SKUs rather than one GPU architecture.

AWS Trainium, Meta custom, and the rest fill the remainder, often on CoWoS-R or smaller CoWoS-S/L depending on HBM count. This is where a missed allocation shows up as a delayed custom-silicon rack, not as a missing H100 equivalent on a public cloud price list.

The fight is not about who has a better slide. It is about who booked 2026 and 2027 reconstructed wafers when the interposer area per GPU jumped.

A realistic timeline

One useful heuristic: ask which variant (-S, -L, -R), how many reticle-multiples, how many HBM stacks, and whether the compute is one die, two, or a SoIC stack. Do not ask whether the company "uses advanced packaging." Everyone serious does.

The bottom line

2026 is the year CoWoS stopped being a TSMC specialty line that a few FPGA and GPU customers used, and became the chokepoint for the AI accelerator industry.

The physics is old. Reticle-limited dies and HBM cubes need millimeters of dense copper, not centimeters of board. Silicon interposers (CoWoS-S) did that first. They ran out of cheap area around 3.3× reticle. RDL (CoWoS-R) buys area and compliance. LSI bridges in an RDL interposer (CoWoS-L) buy silicon-density wiring without a 5.5× slab of TSV silicon. NVIDIA's two-reticle, 208-billion-transistor, 10 TB/s Blackwell GPU is that last product in volume. EUV printed the transistors. CoWoS made them a GPU.

For anyone making decisions today, the split is clean. If the question is what sits under a 2026 flagship training GPU, you are looking at CoWoS-L, eight HBM stacks, and a fight for the next reconstructed wafer. If the question is whether a vendor's "advanced packaging" story is CoWoS, ask which variant, which reticle multiple, and whether the HBM is on that package. If the question is whether the shortage is 2 nm or nanosheets, it is not — not for the accelerators shipping this year. The transistor node is the next problem. The assembly slot is this year's.

Frequently asked questions

What does CoWoS stand for?

Chip-on-Wafer-on-Substrate. Dies are attached to an interposer wafer (CoW), then that assembly is attached to an organic package substrate (WoS). TSMC's registered name for its 2.5D family.

What is the difference between CoWoS-S, CoWoS-L, and CoWoS-R?

CoWoS-S uses a full silicon interposer (up to 3.3× reticle, ~2,700 mm²). CoWoS-R uses an RDL (polymer/copper) interposer, volume since 2023, 4 µm minimum pitch. CoWoS-L uses an RDL interposer plus embedded local silicon interconnect bridges for silicon-density die-to-die and die-to-HBM links, 3.5× in volume since 2024 and 5.5× in production in 2026.

Is CoWoS the same as a silicon interposer?

Only CoWoS-S is a full silicon interposer. CoWoS-R is not. CoWoS-L uses silicon locally (LSI) and RDL for the rest. Saying "silicon interposer" when you mean Blackwell is usually wrong.

How is CoWoS different from Intel EMIB?

EMIB embeds silicon bridges in an organic substrate and skips a reconstructed interposer wafer. CoWoS-L is the closest TSMC equivalent: silicon bridges plus an RDL interposer built as a wafer-level product. EMIB can be a large rectangle; CoWoS is built on round reconstructed wafers until panel-level flows arrive. NVIDIA's 2026 flagship GPUs use CoWoS, not EMIB.

How is CoWoS different from SoIC?

SoIC is 3D hybrid bonding (dies stacked face-to-face or face-to-back, sub-10 µm pads). CoWoS is 2.5D (dies side by side on an interposer). TSMC's own description is that a SoIC stack can then be assembled with CoWoS. They compose. They do not substitute.

Why do NVIDIA, AMD, and Broadcom compete for CoWoS?

Because the large AI packages — dual-reticle GPUs, Instinct, TPUs, custom XPUs — all need a dense 2.5D interposer and HBM shoreline that TSMC's CoWoS line currently dominates. Capacity is finite. A dual-die CoWoS-L part uses more interposer area than an older CoWoS-S part, so GPU units do not scale 1:1 with "CoWoS wafers."

How big is 5.5-reticle or 14-reticle CoWoS?

A scanner reticle is about 26 × 33 mm (~858 mm²). TSMC quotes CoWoS-S at 3.3× ≈ 2,700 mm². 5.5× is in production in 2026. 14×, targeted for 2028, is sized in TSMC's symposium language for about 10 large compute dies and 20 HBM stacks. Those are interposer envelopes, not logic-die sizes.

Is CoWoS sold out through 2026?

TSMC does not publish a booked-versus-capacity table. Wei's July 2026 statement that packaging capacity limits customer growth is the primary-source version of "sold out." Analyst notes describing CoWoS-S and CoWoS-L as fully booked, with NVIDIA around 60% of demand, are consistent with that but are not company numbers.

Will Arizona packaging fix this?

Not in 2026. TSMC's additional Arizona commitment includes advanced-packaging fabs, and Wei described a multi-year US build. Taiwan — Chiayi, Tainan, Zhunan, and the rest of the AP fleet — is where 2026–2027 CoWoS wafers actually come from.

Methodology

This guide is based on primary foundry, customer, and government disclosures available as of 18 August 2026: TSMC's CoWoS technology page (CoWoS-S to 3.3×-reticle / ~2,700 mm²; CoWoS-R RDL interposer in volume since 2023 with 4 µm minimum pitch, 2 µm line/space, GSGSG shielding, CTE-buffer language; CoWoS-L RDL + LSI + eDTC, first 3.5× in volume since 2024; recommendation to use -L or -R above 3.3×); TSMC's 22 April 2026 North America Technology Symposium release (5.5-reticle CoWoS now in production; 14-reticle CoWoS with ~10 large compute dies and 20 HBM stacks slated for 2028; beyond 14 reticles in 2029; 40-reticle SoW-X in 2029; A14-to-A14 SoIC in 2029 at 1.8× I/O density vs N2-on-N2; COUPE-on-substrate production in 2026); TSMC's SoIC technology page (sub-10 µm bond pitch, 3 nm stacking in volume 2025, SoIC as a front-end stack subsequently assembled in CoWoS/InFO/SoW); TSMC Q2 2026 earnings (16 July 2026): C.C. Wei that packaging capacity "is so tight that now it limits my customers' growth," CoWoS still the majority of advanced packaging, glass-substrate alternative on a pilot line needing about one more year to mature, 10–20% of 2026 capex for advanced packaging/testing/mask/others, 13 leading-edge and advanced-packaging fabs in Taiwan, additional Arizona investment including advanced-packaging fabs; 2Q26 HPC mix of 66% of revenue from TSMC's earnings materials. NVIDIA's Blackwell architecture page (208 billion transistors, TSMC 4NP, two reticle-limited dies, 10 TB/s chip-to-chip interconnect as one GPU) and NVIDIA's Blackwell Ultra technical blog (288 GB HBM3e, eight 12-Hi stacks, 8 TB/s, dual-die 208B transistor compute). Taiwan NSTC minister Wu Cheng-wen, 12 July 2026, Chiayi Science Park Phase II groundbreaking: two Phase I advanced-packaging facilities in mass production as of June 2026; three additional TSMC AP facilities planned in ~90 ha Phase II. IEEE ECTC 2021 "Wafer Level System Integration of the Fifth Generation CoWoS-S with High Performance Si Interposer at 2500 mm²" is cited as a conference disclosure of interposer scale, not as a 2026 product datasheet. Absolute CoWoS wafers-per-month, NVIDIA/AMD/Broadcom percentage allocations, and AP8 Tainan floor-area figures are industry and sell-side estimates and are labeled as such; TSMC does not publish those numbers in the documents above. Reticle geometry (~26 × 33 mm, ~858 mm²) is the standard 193 nm ArF scanner field used across foundry and packaging literature.