High-NA EUV: A Full Guide to ASML’s 0.55 Optics and Why Most Chips Still Use 0.33

Last updated: October 2026

High-NA EUV is not a new color of light, and it is not a new foundry. It is a fatter cone of the same 13.5-nanometer photons, focused by a new ZEISS column, so that a single exposure can print features a Low-NA scanner would rather split across two or three masks. The product the fab buys is still a TWINSCAN. The thing that changed is the numerical aperture: 0.55 instead of 0.33, anamorphic 4×/8× optics instead of a 4× square shrink, an 8 nm resolution claim instead of 13 nm, and a reported price of at least €350 million, about twice a Low-NA EUV tool.

That split exists because the alternative ran out of k1. For six years, every leading-edge logic die and a growing share of DRAM has been printed on ASML’s NXE platform: 0.33 NA, 13 nm, 26 × 33 mm field, ~65 Low-NA tools shipping in 2026. When 0.33 could not resolve a pitch, the industry did what it always does: double patterning, computational lithography, more overlays, more cycle time. High-NA is the other knob on the Rayleigh equation. It is also a half-field machine that stitches large dies, a 175-wafer-per-hour production SKU that Intel accepted, and a cost argument TSMC’s Kevin Zhang summarized in one clause in April 2026: “very, very expensive.”

What changed in 2026 is not that High-NA was invented. Intel integrated the first commercial EXE:5000 in Hillsboro in 2024; SK hynix assembled an EXE:5200B at M16 in September 2025; ASML’s own 2024 story already promised high-volume manufacturing in 2025–2026. What changed is that, on 15 July 2026, ASML confirmed Intel Foundry is using High-NA on selected Intel 18A layers of a subset of Core Ultra Series 3 (Panther Lake), dual-qualified against the NXE fleet, at yields ASML says match Low-NA, while TSMC, which prints most of the world’s AI accelerators, told reporters it will harvest 0.33 through A12/A13 in 2029. The useful question is not “is High-NA real.” It is which layers it actually prints, which dies still fit a 26 × 16.5 mm field, and whether a second pass of a depreciated NXE:3800E is still cheaper than a €350 million EXE.

This is the dedicated High-NA guide. The tin-plasma source, the vacuum column, and the Low-NA volume business live in the EUV lithography full guide. We do not re-derive them here.

Key takeaways

• High-NA is an optic, not a wavelength. NXE and EXE both use 13.5 nm light. Raising NA from 0.33 to 0.55 is a 1.67× jump. ASML’s quoted resolution moves from about 13 nm to about 8 nm (16 nm pitch in a single exposure, per imec). The 1.7× smaller-feature / 2.9× density numbers on the EXE product pages are a theoretical ceiling for the layers that actually use the extra contrast, not a chip-level multiplier on an 18A or N2 die.
• Anamorphic optics keep the 6-inch reticle and cut the field in half. A uniform 8× shrink would have forced a larger mask blank. ZEISS instead demagnifies 4× in x and 8× in the scan direction. IEEE Spectrum’s ASML write-up of the design is the public geometry: 26 × 16.5 mm on the wafer instead of 26 × 33 mm. Large chiplet dies stitch two half-fields. That is a design and OPC problem, not a poster.
• EXE:5000 is the research tool. EXE:5200B is the production SKU. Intel accepted the 5200B at 175 wafers per hour and 0.7 nm overlay. Throughput is quoted at 50 mJ/cm²; Low-NA NXE:3800E is quoted at 220 wph at 30 mJ/cm². Dose, half-field, and overlay are the three numbers that decide whether High-NA beats another Low-NA pass.
• 2026 High-NA is a beachhead, not a fleet. ASML recognized revenue on one High-NA system in Q2 2026 and is shipping around 65 Low-NA tools this year. Intel is first to ship a high-volume logic product with High-NA layers: selected 18A layers, a subset of Panther Lake, dual-qualified. SK hynix assembled the first memory EXE:5200B. TSMC owns High-NA for R&D and is not putting it in A12/A13 HVM. Most chips still use 0.33 because the multi-patterning bill has not yet exceeded the tool bill. At TSMC’s wafer volume, a depreciated NXE plus extra masks can still undercut a €350 million ($410 million, Bloomberg’s April 2026 figure) EXE. High-NA is required when a pitch cannot be printed in a tolerable number of Low-NA exposures, or when overlay and cycle time on those extra passes blow the node. It is optional, and currently declined, for TSMC’s 2026–2029 logic.
• The scanner does not retire CoWoS, HBM, or GAAFET. High-NA prints the densest layers of a nanosheet transistor and, eventually, of the DRAM that becomes HBM. It does not assemble the package. A better critical-layer CD on a die that cannot get a CoWoS slot is unfinished inventory.

High-NA EUV at a glance

What High-NA actually is

Start with the thing it is not. It is not a second EUV invention. The light is still a laser-produced tin plasma at 13.5 nm. The reticle is still a multilayer reflector. The column is still mirrors in vacuum. If you need the droplet, the collector, and why glass does not work, that guide is the primary. High-NA is the next knob after wavelength.

Photolithography resolution is the Rayleigh criterion: CD ≈ k₁ × λ / NA. λ is already at 13.5 nm. k₁ is a process factor the industry has spent twenty years squeezing with illumination, masks, resists, and multiple patterning. NA is how wide a cone of diffracted light the projection optics can collect. NXE tools sit at 0.33. EXE tools sit at 0.55. That is a 67% increase in NA, and it is why ASML’s product pages move the resolution claim from 13 nm to 8 nm.

imec’s long-form High-NA note is the cleanest public translation into pitch: 8 nm resolution is 16 nm pitch lines and spaces in one exposure. Low-NA high-volume manufacturing was already near 13 nm (26 nm pitch) as a single-exposure floor. Everything tighter on 0.33 is a multi-patterning conversation: extra masks, extra etches, extra overlay, extra opportunities to put a defect on a GAAFET nanosheet or a buried power rail.

ASML then sells the extra NA two ways, and they are not the same purchase order.

Print smaller. Features 1.7× smaller, transistor densities 2.9× higher, “40% more imaging contrast than NXE.” Those figures are on the EXE:5000 and EXE:5200B pages. They apply to the layers that actually use the extra resolution. They do not mean an Intel 18A or TSMC N2 chip is 2.9× denser because one scanner in the line has a 0.55 column.

Print the same pitch with fewer passes. Higher contrast at a given pitch lets you drop a double-patterning pair back to a single exposure, cut overlay stack-up, and buy back cycle time. Intel’s 2026 insertion is this kind of use: selected 18A layers, dual-qualified so the same product can still run on the NXE fleet. That is a manufacturing option. It is not a node rename.

Depth of focus is the bill the poster omits. DOF falls with the square of NA. imec’s process work is explicit: thinner resists (under ~20 nm) to keep aspect ratio near 2:1 and to live inside a 2–3× smaller focus budget, new hard masks, and metrology that can still see an 8 nm line in 15 nm of resist. A High-NA PO is a resist, etch, mask, and OPC program. The scanner is necessary. It is not sufficient.

Why 0.33 ran out of room

The congestion is not a slogan. It is k₁, overlay, and a mask count.

Single-exposure floor. A 0.33 NA, 13.5 nm tool with a manufacturable k₁ prints about 13 nm. imec and ASML pushed 0.33 to 24 nm pitch lines in the lab; high-volume logic has been living near 26–28 nm pitch for the tightest metal. Below that, 0.33 does not refuse to print. It refuses to print once.

The multi-patterning tax. Two Low-NA exposures can define a pitch one exposure cannot. The costs are literal: a second mask, a second pass through a scarce scanner, an etch, and an overlay budget that now includes the matching of two High-NA-class layers that were supposed to be one. Cycle time stretches. Defect opportunity doubles. Computational lithography (inverse lithography, source-mask optimization, TSMC’s cuLitho-class stack) can recover some of that. It cannot recover a second trip through the track.

Why TSMC can still say no. At the 2026 North America Technology Symposium, TSMC deputy co-COO Kevin Zhang told reporters the company can “harvest the benefit from current EUV” through A12 and A13 in 2029, and that High-NA is “very, very expensive.” Bloomberg put the tool at upwards of €350 million ($410 million). That is a cost-per-exposure argument from the foundry that runs the most NXE hours on earth. Extra Low-NA passes on a depreciated 0.33 fleet, at TSMC’s utilization, can still beat a new half-field machine that costs roughly 2× a current NXE. Intel, with fewer Low-NA hours and a 14A node designed around 0.55, draws the opposite curve.

What “required” actually means. High-NA is required when the pitch and the overlay cannot be closed with a tolerable number of 0.33 passes, or when the extra passes blow the module’s cycle time past the fab’s output target. It is not required to ship a 2026 AI GPU. Those dies are printed on Low-NA, assembled on CoWoS, and stacked with HBM. Treating High-NA as a 2026 supply-constraint on NVIDIA or AMD wafers is a category error.

Anamorphic optics, half-fields, stitching

The headline advance is a fatter cone. The engineering advance is that a fatter cone at the wafer would have been an illegal cone at the mask.

IEEE Spectrum, in an ASML-authored explainer, is the primary public geometry. Increase NA and the angle of incidence at the reticle grows. EUV masks are multilayer mirrors; past a point they stop reflecting and the 3D absorber topography (shadowing, best-focus shifts) eats the process window. The brute-force fix is 8× demagnification and a larger mask blank. That would have forced the mask industry off the 6-inch standard. ZEISS instead built an anamorphic lens: 4× in one direction, 8× in the scan direction. The 6-inch reticle stays. The pattern on the mask is stretched. The field on the wafer halves, about 26 × 16.5 mm instead of 26 × 33 mm.

ASML’s own five-things note is the productivity half of the same sentence. Twice as many exposures per wafer would have halved throughput. The EXE wafer stage accelerates at 8g, twice the NXE; the reticle stage at 32g, four times the NXE. That is how a half-field tool is supposed to remain economical. It is also why “wafers per hour” on an EXE spec sheet is not comparable to an NXE spec sheet until you fix dose and field.

Stitching. A mobile SoC often fits in a half-field. A large AI compute die, a big GPU reticle-scale chiplet, or a 26 × 33 mm-class product does not. Two half-fields are exposed and joined. SPIE/JM3 work from the imec–ASML High-NA Lab (EXE:5000 wafer data, 26 × 16.5 mm², OPC for aerial-image interaction, black-border proximity, stray light) is the experimental record that stitching is possible at 0.55. “Possible” is not “free.” In-die stitching is a design rule, a cut, a double-exposure OPC model, and an overlay spec across a seam. Intel’s SPIE 2026 language called it the half-field challenge and put EDA partners on seam solutions. For chiplet products that already split at the reticle limit, the seam is another partition. For a monolithic die that assumed 26 × 33 mm, it is a layout rewrite.

Pellicles and mask 3D. An 8× direction reduces power density on the mask and pellicle, which imec flags as a High-NA gift. The rest of the mask story is not a gift: thinner, higher-k or low-n absorbers to cut 3D effects inside a smaller depth of focus, CNT pellicles aimed past 600 W, multilayer aging that now prints as stochastic risk. High-NA without a mask program is a column in a crate.

EXE:5000, EXE:5200B, and the Low-NA it has to beat

Two dose numbers belong in the same paragraph. Low-NA throughput is specified at 30 mJ/cm². High-NA throughput is specified at 50 mJ/cm². Contrast can, in principle, let a process run a lower dose at a given pitch; the spec sheet does not assume that gift. Anyone comparing 220 wph to 175 wph without the millijoules is comparing two different exams.

Intel’s foundry blog on 5200B acceptance is the production-spec primary: 175 wafers per hour, 0.7 nm overlay, same 8 nm resolution as the 5000, first commercial High-NA tool to Oregon in 2023–2024. ASML’s 15 July 2026 High-NA HVM release adds that Intel was first to install and pass acceptance on the 5200B. Treat 175 wph and 0.7 nm as machine specs, not as a process-of-record yield audit.

The 5000 remains the tool you develop on. ASML’s January 2024 story said customers would start R&D in 2024–2025 and move into HVM in 2025–2026, with EXE:5000 “more than 185” wph and a 220 wph roadmap. The production SKU that actually took an Intel acceptance test is the 5200B at 175. Use the later number for 2026 capacity math.

NXE does not freeze. The NXE:3800E shares a bottom module (wafer handler, faster stages, higher-power source) with the EXE platform. That is ASML’s commonality pitch: Low-NA gets faster while High-NA gets sharper. TSMC’s 2029 Low-NA plan is a bet that this common module, plus multi-patterning, plus computational lithography, is enough.

Cost: a €350 million-plus class tool

ASML does not put a list price in the 10-Q. The industry-reported band is consistent enough to use as a band, and not consistent enough to send to procurement.

Bloomberg, reporting Zhang at the April 2026 TSMC symposium, put High-NA at upwards of €350 million ($410 million) apiece. In September 2026, heise put a single unit at at least €350 million, about twice as much as previous Low-NA EUV systems. This guide treats High-NA as a ~$350 million-plus class tool, which is what the reporting supports. It is not an ASML quote.

Cost per wafer is the number that matters, and it is not 2×. Inputs:

• Depreciation. A €350M+ tool against a €180M tool, before you count the extra masks you hope to delete.
• Field. Half-field means more exposures per 300 mm wafer unless the 8g/32g stages fully recover it. The 175 wph spec is the recovery claim, at 50 mJ/cm².
• Dose and source. More millijoules is more time over the slit, unless contrast lets you cut dose. Stochastic noise at 8 nm pushes dose up, not down.
• Multi-patterning credit. The whole economic case is “delete two Low-NA passes and their overlay.” On layers where you cannot delete them, High-NA is a more expensive way to print the same pitch.
• Utilization. TSMC’s NXE fleet is the most utilized on earth. Intel’s High-NA tools spent 2024–2025 learning. A learning tool has a terrible cost per wafer; a dual-qualified HVM layer on a 5200B is the first time that sentence starts to change.

Zhang’s “very, very expensive” is this arithmetic from the foundry that would have to buy the most of them. Intel’s 18A dual-qualification is the same arithmetic from the foundry that bought them first and now needs 14A to be a process, not a press release.

Who has one in 2026

Honest install base, not a TAM slide. High-NA tools in the world in August 2026 are counted in the low teens at most, against around 65 Low-NA systems shipping this year. Q2 2026 recognized one High-NA system in EUV net sales of €3.8 billion. Low-NA is still the business.

Intel, in one paragraph. The Hillsboro EXE:5000 was 165 tons, 250+ crates, 43 containers. Intel said then it would use 0.33 and 0.55 together, with proof points on 18A and production into 14A. The 15 July 2026 ASML note is the proof point landing: Naga Chandrasekaran: qualify High-NA as a process option on select 18A product layers so the existing fleet can raise output, while 14A gets the density and flexibility. Dual-qualified means Intel can take the layer off High-NA tomorrow and still ship. That is the opposite of a forced conversion, and it is why “Panther Lake is a High-NA chip” is wrong.

TSMC, in one paragraph. April 22, 2026, North America Technology Symposium. A16 volume aligned to 2027 (ready 2026, ramp with customers 2027). A14 and N2U in the 2028 window. A13 and A12 in 2029, explicitly without High-NA. Zhang: amazed R&D can keep scaling without it; “one day they may have to use it.” In September 2026 TSMC put a date on that day: High-NA in high-volume manufacturing for advanced nodes starting in 2030. The same company is expanding CoWoS because packaging, not a 0.55 column, is the 2026 AI GPU gate. That allocation is internally consistent.

Memory. SK hynix’s 3 September 2025 newsroom item is the primary: EXE:5200B at M16, 0.55 vs 0.33, 1.7× / 2.9× ASML figures repeated, intent to simplify existing EUV process for next-generation DRAM. HBM is still a stacking and packaging problem first. High-NA on DRAM is how you print a tighter cell when 0.33 multi-patterning on the critical layers runs out, the same sentence as logic with a different tapeout calendar.

September 2026 update: one million Intel wafers, TSMC’s 2030 date, and 12-inch masks

Two September 2026 announcements, both timed to the SPIE Photomask Technology and EUV Lithography conference, moved this guide’s central fork. On 7 September, Intel Foundry and ASML said Intel has processed more than one million wafers with High-NA across tool certification, R&D, and volume production on select layers of a subset of Core Ultra Series 3 (Panther Lake). Intel says overlay, throughput, and availability are meeting its expectations, and that 18A products using High-NA on those layers perform at or above the comparable NXE-patterned layers. Customers can use High-NA on today’s 6-inch masks by floor-planning inside the half-field or by using Intel’s stitching and PDK support. heise’s analysis notes that most Panther Lake compute dies are still likely made on Low-NA with multi-patterning. Dual qualification remains the story.

On 8 September, ASML and TSMC announced an initiative to move the industry to 12-inch photomasks, targeting a 12-inch mask pilot line by 2031 and 12-inch High-NA systems in advanced-node production by 2033. In the same release, TSMC said it intends to use High-NA in high-volume manufacturing for advanced nodes starting in 2030, first on current 6-inch masks, and expects the number of High-NA layers to rise as transistor architectures get more complex.

Inside Deep Tech’s take: the April position (no High-NA through A12 and A13 in 2029) still holds, but TSMC now has a High-NA HVM year, 2030. The 12-inch mask effort is also the clearest admission yet that the half-field is a real cost: the stated goal is to remove stitching constraints, which is why stitching is still the open question for large AI dies. None of this changes how a 2026 AI GPU is printed. It is still Low-NA, then CoWoS, then HBM.

October 2026 refresh: Physical AI demand and the EUV companion guide

The September 2026 marks still stand. Intel Foundry and ASML said on 7 September 2026 that Intel has processed more than one million High-NA wafers across certification, R&D, and volume production on select Core Ultra Series 3 (Panther Lake) 18A layers. ASML and TSMC's 8 September photomask release keeps TSMC's High-NA HVM intent at 2030, with a 12-inch mask pilot line targeted for 2031 and 12-inch High-NA production readiness by 2033.

What October adds is the demand sandwich around those scanners. AI racks that need High-NA-patterned logic still have to clear CoWoS slots (see the CoWoS full guide) and still land in liquid-cooled halls. For the robot and Physical AI side of that demand, see the Physical AI Market Report: October 2026. For the Low-NA volume business High-NA still sits on top of, keep the EUV lithography full guide open next to this page.

When High-NA is actually required

A short mapping, because the slides will not provide one.

The honest heuristic: if deleting two Low-NA passes pays for the EXE, the overlay, the half-field stitching, and the thinner-resist etch stack, High-NA is required for that layer. If it does not, 0.33 is still the printer. Most layers on most chips, including most layers on an 18A Panther Lake die, fail that test today. That is not a failure of High-NA. It is what “selected layers” means.

What still breaks

Cost per exposure at TSMC volume. Until an EXE’s good-wafer cost undercuts a second NXE pass, the world’s largest foundry will keep saying no. Zhang already did. ASML’s High-NA revenue in a quarter where it sold 86 new lithography systems was one tool. That is the 2026 demand signal.

Half-field and stitching on AI-sized dies. The dies that most need density, accelerator compute chiplets approaching the reticle limit, are the dies that most need a seam. OPC at the stitch, black-border flare, and a design partition that does not put a critical gate on the join are 2026 papers, not 2019 slogans.

Depth of focus, resists, stochastics. 8 nm lines in <20 nm of resist, MOR vs CAR, line collapse, photon shot noise at higher NA. imec’s High-NA program is mostly this, not the column. A 175 wph spec assumes a dose and a resist that yield.

Pellicles, mask 3D, inspection. High-NA without a high-transmission pellicle that survives the 32g reticle stage is a particle magnet. Mask 3D at 0.55 incidence is why anamorphic exists; residual 3D is why new absorbers exist. Inspection of 8 nm defects is an e-beam throughput problem.

Install and availability. 150-plus metric tons, months of calibration, a cleanroom module (Intel’s Mod 3). A 2026 PO does not become a 2026 wafer. Dual-qualification is how Intel refused to let that sentence gate Panther Lake.

It does not shrink the back-end bill. CoWoS slots, HBM stacks, and UCIe assembly still sit after the scanner. High-NA can make a denser GAAFET layer. It cannot unscrew a packaging queue.

A realistic timeline

One useful heuristic: watch dual-qualified layers and wafers per day, not press-release numerical apertures. A generation that prints in volume at matched yield is the generation that matters. 0.55 cleared that bar on a handful of Intel 18A layers in July 2026. It has not cleared it as a foundry-wide default.

The bottom line

2026 is the year High-NA EUV became a production option, and the year most chips, including most AI chips, still used 0.33.

The physics is a fatter cone of the same 13.5 nm light: 0.55 NA, 8 nm instead of 13 nm, 4×/8× anamorphic optics so the mask industry could keep a 6-inch reticle, a half-field that stitches, stages at 8g and 32g so throughput does not collapse, a 175 wph / 0.7 nm 5200B that Intel accepted, and a €350 million-plus class price that TSMC declined to put on the HVM line through 2029. Intel is shipping selected 18A layers on that tool, dual-qualified, on a subset of Panther Lake. SK hynix has a 5200B in Icheon. ASML recognized one High-NA system in a quarter when it still guided ~65 Low-NA tools for the year.

For anyone making decisions today, the split is clean. If the question is how 2026 AI silicon is printed, you are looking at Low-NA NXE, then CoWoS, then HBM: the EUV volume story, not this one. If the question is whether a 14A-class foundry pitch is real, ask how many critical layers are single-exposure 0.55, whether they are dual-qualified or mandatory, and whether the die fits 26 × 16.5 mm without a stitch. If the question is whether TSMC “falling behind on High-NA” matters this year, the answer is no, unless you needed a 16 nm-pitch single exposure that 0.33 cannot close. The NA in the press release will not answer it.

Related Inside Deep Tech full guides: the EUV lithography guide covers the Low-NA volume business, GAAFET nanosheets and backside power delivery are the transistor and power layers High-NA will pattern, and CoWoS and hybrid bonding are where those dies get assembled. The same AI buildout drives co-packaged optics (CPO), silicon photonics, and 800 VDC power distribution in the data center.

Related: the companion EUV lithography guide, CoWoS packaging, and the Physical AI Market Report: October 2026.

Frequently asked questions

What is High-NA EUV?

An ASML EXE-platform scanner that prints with the same 13.5 nm EUV light as Low-NA NXE tools, but with projection optics at 0.55 numerical aperture instead of 0.33. Quoted resolution moves from about 13 nm to about 8 nm (16 nm pitch in a single exposure). The EXE:5200B is the high-volume SKU.

How is 0.55 NA different from 0.33 NA?

NA is how wide a cone of light the lens collects. 0.55 / 0.33 ≈ 1.67×. That is the entire optical bet. Wavelength does not change. The price of the fatter cone is anamorphic optics, a half-size field, thinner resists, and a tighter depth of focus.

Why anamorphic 4×/8× instead of a bigger mask?

A uniform 8× shrink would have needed a larger reticle blank and broken the 6-inch mask ecosystem. ZEISS demagnifies 8× only in the scan direction, 4× in the other, so the mask stays 6 inches and the wafer field becomes 26 × 16.5 mm. IEEE Spectrum’s ASML explainer and imec’s High-NA article are the primaries.

Does High-NA replace Low-NA?

No. ASML is shipping around 65 Low-NA systems in 2026 and adding 30% Low-NA capacity in 2027. High-NA is an option for the hardest layers. Intel’s 18A insertion is dual-qualified against NXE. TSMC’s 2029 nodes as presented do not require it.

Is Intel’s Panther Lake a High-NA chip?

No. ASML’s 15 July 2026 release is specific: a subset of Core Ultra Series 3, selected Intel 18A layers, dual-qualified, yields matched to NXE, product shipping. Regular 18A production still runs on Low-NA. High-NA is a process option on some layers of some units.

Why won’t TSMC use it yet?

Cost. Kevin Zhang, April 2026: current EUV can still be harvested; High-NA is “very, very expensive”; A12/A13 in 2029 are not High-NA nodes. At TSMC volume, extra 0.33 passes plus computational lithography still beat a €350 million-plus half-field tool. They own High-NA machines for research. In September 2026 TSMC said it intends to use High-NA in high-volume manufacturing starting in 2030, first on today’s 6-inch masks, and launched a 12-inch mask initiative with ASML.

How much does a High-NA scanner cost?

ASML does not list it. Industry reporting clusters at €350 million and up: Bloomberg’s $410 million, heise’s “at least €350 million,” about twice Low-NA. Treat it as a $350 million-plus class tool, not a purchase-order number.

What throughput does EXE:5200B actually have?

Intel’s accepted spec, which ASML has used in public: 175 wafers per hour at the High-NA dose convention (50 mJ/cm²) and 0.7 nm overlay. NXE:3800E is ≥220 wph at 30 mJ/cm². Do not compare those two integers without the millijoules and the field size.

What changed for High-NA EUV in September 2026?

Intel said it has processed more than one million High-NA wafers, including volume production on select 18A layers, and TSMC said it will use High-NA in high-volume manufacturing starting in 2030 while launching a 12-inch photomask initiative with ASML (pilot line by 2031, production readiness by 2033).

Does this replace the EUV full guide?

No. That guide is the tin plasma, the vacuum column, the Low-NA volume business, export controls, and ASML’s 2026 shipment math. This one is the 0.55 column, the anamorphic field, the 5000/5200B split, and the Intel/TSMC fork.

Methodology

This guide is based on primary vendor, foundry, and peer-reviewed disclosures available as of 24 August 2026, refreshed in September 2026 with Intel Foundry’s 7 September 2026 High-NA update (more than one million wafers), the 8 September 2026 ASML and TSMC 12-inch mask release (TSMC High-NA HVM from 2030), and heise’s September 2026 price reporting; unsourced secondary price bands were removed. ASML’s EXE:5000 and EXE:5200B product pages (0.55 NA, 8 nm resolution, 40% more contrast than NXE, 1.7× / 2.9× claims, anamorphic optics, half-size field vs NXE, EXE:5200B as successor with improved source and ZEISS projection optics) and the 25 January 2024 “5 things you should know about High NA EUV” note (first EXE:5000 modules to Intel December 2023; 4×/8× anamorphic to keep traditional reticles; 8g wafer / 32g reticle stages; R&D 2024–2025, HVM 2025–2026 as then-stated) are the optics primaries. ASML’s NXE:3800E page (0.33 NA, 13 nm, ≥220 wph at 30 mJ/cm², bottom module common with EXE) is the Low-NA comparison primary. ASML’s 15 July 2026 “High NA EUV reaches new readiness milestone with first high-volume Logic product” (Intel Foundry using EXE High-NA on Intel 18A for a subset of Core Ultra Series 3 / Panther Lake; specific layers dual-qualified in Oregon; yields matched to NXE; first commercial High-NA integrated 2024; Intel first to install and accept EXE:5200B) is the HVM primary. ASML’s 15 July 2026 Q2 results (€9.3 billion sales, 54% gross margin, ~65 Low-NA EUV and ~130 DUV immersion in 2026, +30% Low-NA capacity planned 2027) plus Q2 investor-call remarks the same day (€3.8 billion EUV system sales including one High-NA system) are the shipment primaries. Intel Foundry’s High-NA newsroom item on the Hillsboro EXE:5000 (165-ton tool, 0.33 and 0.55 used together, 18A proof points then 14A) and Intel’s EXE:5200B acceptance language (175 wph, 0.7 nm overlay) are the Intel primaries. SK hynix’s 3 September 2025 newsroom release (EXE:5200B assembled at M16 Icheon, first High-NA for memory mass-production intent) is the memory primary. imec’s High-NA longread (0.55 NA, 8 nm / 16 nm pitch single exposure, 4×/8× anamorphic, half field, stitching, DOF ~2–3× down, thinner resists) and IEEE Spectrum’s High-NA optics explainer (26 × 16.5 mm vs 26 × 33 mm, anamorphic rationale) plus JM3/SPIE stitching papers on EXE:5000 wafer data are the independent technical primaries. TSMC’s April 2026 North America Technology Symposium remarks as reported by Bloomberg and Tom’s Hardware (Kevin Zhang: harvest current EUV; High-NA “very, very expensive”; A12/A13 2029 without High-NA; tool “upwards of €350 million / $410 million”) are the TSMC primaries; TSMC does not file a High-NA list price, and this guide does not invent one. High-NA list prices, non-Intel HVM insertion dates, and any Samsung Hwaseong EXE:5000 details not in a Samsung newsroom item are labeled as industry-reported. Overlay and 175 wph figures are company-stated machine specs, not independent yield audits. Tin-plasma source physics, Low-NA export controls, and the 2026 NXE volume business are cross-referenced to the 17 August 2026 EUV full guide, not re-derived.