CXL Memory Pooling: A Full Guide to Compute Express Link in AI Servers

Compute Express Link is not a new kind of DRAM, and it is not a replacement for HBM. It is a cache-coherent protocol that rides the same physical layer as PCI Express: three multiplexed channels — CXL.io, CXL.cache, and CXL.mem — that let a CPU treat memory sitting on an add-in card, an E3.S bay, or (on paper) a rack-scale switch as part of its address map. The product the operator buys in 2026 is almost always a Type-3 memory expander. The slide the vendor shows is often a fabric.

That gap is the story. HBM is package-local: eight stacks a few millimeters from a GPU on a CoWoS interposer, hundreds of gigabytes at several terabytes per second. DDR5 is socket-local: twelve channels on a Xeon 6, maybe 1–2 TB if you fill every DIMM. CXL is the next hop. It is slower than those two, much faster than NVMe, and — unlike HBM — it can be added after the package is closed. AI servers care because KV caches, embedding tables, and CPU-side preprocessing overflow local DRAM long before they overflow the GPU's HBM budget, and because a rack that over-provisions DDR on every node is paying for stranded capacity.

What changed in 2026 is not that CXL was invented. The 1.0 spec shipped in March 2019. It is that Type-3 add-in cards and pooling boxes are no longer booth demos, Intel Xeon 6 and AMD EPYC 9005 hosts with CXL 2.0 are in volume, Samsung's CMM-B and Astera Labs' Leo P-series are production SKUs, and the CXL Consortium has already published 3.1, 3.2, and 4.0. The useful question is which of those generations is a shipping device, which is a host CPU, and which is still a white paper.

Key takeaways

• CXL is cache-coherent attach over a PCIe PHY, not a memory technology. The DRAM inside a Type-3 module is ordinary DDR5. The protocol is what makes that DRAM appear in the CPU's physical address space with load/store semantics instead of as a block device. Chiplets and UCIe solve die-to-die inside a package. CXL solves host-to-device across a connector.
• Three protocols, three device types, and they are not interchangeable. CXL.io is PCIe-like configuration and DMA. CXL.cache lets a device cache host memory. CXL.mem lets the host cache and access device memory. Type 1 uses .io + .cache, Type 2 uses all three, Type 3 uses .io + .mem. Almost every 2026 SKU you can order is Type 3.
• Pooling, sharing, and tiering are different products. Pooling (CXL 2.0) assigns exclusive slices of a memory device to different hosts. Sharing (CXL 3.0) lets more than one host map the same coherent region at once. Tiering is a software or CPU-hardware policy that puts hot cachelines in local DDR and cold ones in CXL. Intel's Flat Memory Mode on Xeon 6 is the hardware-tiering version of that last idea.
• HBM stays on the package. CXL is the next hop. A Blackwell-class GPU still gets its working set from HBM on CoWoS. CXL does not sit in that path. Where it pays in AI is CPU-attached capacity and bandwidth: DLRM embedding tables, inference KV-cache overflow, in-memory databases sitting next to GPUs, and not buying 2 TB of DDR5 for a node that needs 512 GB most of the time.
• The 2026 shipping picture is Type-3 cards and CXL 2.0 pooling boxes, not a general fabric. Astera Leo E/P-series and the A1000 add-in card are production CXL 1.1/2.0 controllers. Samsung CMM-D modules and the CMM-B box (Xconn switch, up to 22× E3.S, CXL 2.0) are the memory-side version of the same generation. CXL 3.x fabrics, Global Fabric Attached Memory, and CXL 4.0 at 128 GT/s are real specifications. They are not the bill of materials in a 2026 GPU rack.
• Latency is the tax, and topology decides whether you pay it twice. Academic measurements of ASIC Type-3 expanders sit around 210–270 ns versus ~80–130 ns for local DDR5. Samsung's own CMM-B disclosure at Memcon 2024 put a switch-based pool at 596 ns and ~60 GB/s. Direct-attach expansion can be a bandwidth win. Switch-based pooling is a capacity and utilization win. It is not HBM.

CXL at a glance

What CXL actually is

Start with the thing it is not. It is not HBM. HBM is a stacked-DRAM package with a 1024-bit-class interface that lives on the same interposer as the GPU. It is not UCIe. UCIe is a die-to-die PHY and protocol for chiplets a few millimeters apart; CXL.cache and CXL.mem are host-to-device protocols that tolerate a connector, a retimer, and tens of centimeters of board. And "we support CXL" on a CPU slide does not tell you whether the platform can do pooling, sharing, or just a single Type-3 expander in the PCIe slot.

The CXL Consortium's own language, in the 3.0 white paper by Debendra Das Sharma (Intel) and Ishwar Agarwal (Microsoft), is the right definition: an open interconnect offering high-bandwidth, low-latency connectivity between a host processor and devices such as accelerators, memory buffers, and smart I/O, by enabling coherency and memory semantics on top of PCIe-based I/O. CXL 1.0, March 2019, already had the three protocols. Everything since has been about switching, pooling, sharing, fabrics, and faster PHYs.

The PHY is PCIe. That is the adoption bet. You reuse the connector, the channel, the retimer ecosystem, and a lot of the verification. You do not reuse PCIe as a software model. A CXL.mem transaction is a 64-byte cacheline request with coherency metadata, not a 4 KB NVMe read. The host MMU maps the device's Host-managed Device Memory (HDM) into the physical address space. Loads and stores hit it. The OS may see a new NUMA node, a single interleaved region, or — on Xeon 6 with Flat Memory Mode — one address space that the CPU's hardware pager keeps hot in DDR.

The three protocols

CXL.io. The PCIe-shaped channel. Enumeration, configuration space, DMA, interrupts, error reporting. Every CXL device speaks it, because something has to look like a PCIe function to BIOS and the OS. If you only had CXL.io you would have a smart NIC or a storage controller, not CXL.

CXL.cache. The device is a cache of host memory. A Type-1 accelerator — a NIC, a lookaside crypto engine, something without its own HBM or HBM-like pool — uses this to snoop and cache lines that live in the CPU's DDR. Bias modes in 1.x/2.0, then enhanced coherency with back-invalidate in 3.0, are the machinery. This is not how a 2026 Type-3 DIMM works.

CXL.mem. The host is a cache of device memory. The CPU issues memory requests over the link; the device returns cachelines. This is the Type-3 expander, and it is the 2026 product. Bandwidth is a function of link width and generation: a PCIe 5.0 x8 link is theoretically ~32 GB/s each way, x16 ~64 GB/s. Real Type-3 ASICs in the Melody characterization (ASPLOS) landed between 18 and 52 GB/s depending on lane count and DRAM. That is a fraction of one HBM stack and a useful add-on to a 12-channel DDR5 CPU.

The three protocols time-multiplex on one link. A Type-2 GPU-class accelerator would speak all three: .io to appear, .cache to snoop host memory, .mem so the host can reach the device's HBM. Shipping NVIDIA GPUs in 2026 do not use that path for scale-up. They use NVLink and package-local HBM. Treat Type-2 CXL as an architectural option the spec has carried since 1.0, not as the GPU you can buy this year.

Type 1, Type 2, Type 3

A Type-3 device can be a Single Logical Device (SLD) — one host sees one chunk of memory — or, from CXL 2.0, a Multiple Logical Device (MLD) that carves the physical DRAM into slices for different hosts. That carve-up is pooling. It is not sharing. Sharing, in the 3.0 sense, is hardware coherency on the same bytes.

How the generations actually differ

Vendor copy flattens "CXL" the way it flattens "CoWoS." It is at least five specification generations and two very different topologies.

CXL 1.0 / 1.1: the point-to-point expander

32 GT/s, PCIe 5.0 PHY, 68-byte flits. Type 1/2/3. No switch. One host, one device, coherency via bias modes. Intel Sapphire Rapids (4th Gen Xeon, 2023) and AMD Genoa (EPYC 9004) were the first volume hosts. The device you could buy was a CXL 1.1 Type-3 card: Samsung CMM-D 1.0 in 2022, Micron CZ120 in 2023, early Astera Leo. This generation is still what a lot of "CXL memory" benchmarks actually run, even when the box is newer.

CXL 2.0: switching and pooling

Still 32 GT/s. The new work is a single level of switching, persistent-memory semantics (global persistent flush), security, and memory pooling. A CXL 2.0 switch sits between hosts and Type-3 devices and, with a Fabric Manager, binds downstream memory to upstream ports. Samsung's CMM-B white paper is the cleanest public description of a shipping-class box: a 4U chassis, an Xconn CXL SoC switch, up to 22× E3.S CMM-D modules, CXL 1.1/2.0, Single Logical Device pooling via the Fabric Manager API, up to three hosts, up to 5.6 TB if you fill 22× 256 GB modules. That is a pooling box, not a fabric. One switch, a handful of hosts, exclusive slices.

Intel Xeon 6 (Granite Rapids P-core, Sierra Forest E-core) is the volume 2.0 host. The Hot Chips 2023 architecture disclosure is the primary source: full CXL 2.0 (pooling, interleave, port bifurcation, hot-plug), up to 136 lanes of PCIe 5.0 / CXL 2.0 on the P-core part, and Flat Memory Mode — cacheline-granular hardware tiering so the OS sees one region and hot lines stay in local DDR. AMD EPYC 9005 (Turin) is the other volume 2.0 host; Astera has published interop of Leo with both.

CXL 3.0 / 3.1 / 3.2: fabrics, sharing, and a faster PHY

CXL 3.0, August 2022, moves the PHY to PCIe 6.0: 64 GT/s, PAM-4, 256-byte flits, a latency-optimized flit variant the Consortium says saves 2–5 ns of store-and-forward. Raw x16 bandwidth doubles to 256 GB/s aggregate. The architectural jump is larger than the PHY:

• Memory sharing, distinct from pooling: the same region mapped by multiple hosts, hardware-coherent, no software lock on every line.
• Enhanced coherency replaces bias modes. Type-2 and Type-3 devices can back-invalidate the host cache. Peer-to-peer access to HDM does not have to trombones through the CPU.
• Fabrics, not a tree: Port-Based Routing (PBR) for up to 4,096 nodes, non-tree topologies, and Global Fabric Attached Memory (GFAM) — a Type-3-like device that hangs off a switch node without a dedicated host.

CXL 3.1 (November 2023) is the operations spec on top of that: Global Integrated Memory (GIM) for inter-host communication, a Fabric Manager API for PBR switches, the CXL TEE Security Protocol (TSP) so a Type-3 expander can sit inside a confidential-compute trust boundary, and expander RAS — 34-bit metadata per line, sparing, scrubbing, capacity degradation. The 3.1 white paper is the primary source.

CXL 3.2 adds, among other things, a CXL Hot Page Monitoring Unit (CHMU) so a pool can see which lines are actually hot. Samsung has said it will take CMM-D 3.0 to 3.2 for a late-2026 mass-production target; SK hynix showed a 256 GB second-generation CMM-DDR5 sample at HPE Discover in June 2026. Those are vendor and trade-press statements about devices. They are not statements that Xeon or EPYC hosts with CXL 3.x root complexes are in your rack. The honest 2026 host generation is still 2.0.

CXL 4.0: a spec, not a SKU

On 18 November 2025 the Consortium released CXL 4.0: 128 GT/s on a PCIe 7.0 PHY, bundled ports that aggregate multiple physical links into one logical accelerator, native x2 width for fan-out, up to four retimers, RAS extras, backward compatible to 1.0. Derek Rohde, Consortium president and a NVIDIA principal engineer, called it a milestone for coherent memory connectivity. The 4.0 white paper quotes 768 GB/s each way on a bundled x16-class example, 1.536 TB/s bidirectional. That is a specification envelope. It is not a 2026 CPU, and it is not how you attach HBM to a GPU.

Pooling vs sharing vs tiering vs expansion

Four words get used as synonyms. They are four different designs, and they have four different latency and software stories.

Expansion. One host, one or more Type-3 devices, no switch required. The CPU gains capacity and, if you still had spare CXL lanes after filling DDR channels, bandwidth. This is the Micron CZ122 configuration in the December 2024 Xeon 6 paper: 12 channels of DDR5-6400 (768 GB) plus eight 128 GB E3.S x8 devices (1 TB more) as a unified NUMA node with Linux 6.9+ weighted interleaving. Read-only bandwidth +24%, mixed +39%, geometric-mean workload speedup +24%. Those are the authors' measurements on a 6900P, not a universal KPI. Expansion is the 2026 default because it does not need a fabric manager.

Pooling. A shared device (or a switch full of devices) whose capacity is partitioned across hosts. Host A gets 256 GB, host B gets 512 GB, neither sees the other's pages. CXL 2.0 MLDs and switch-based SLD binding are this. Samsung CMM-B does SLD pooling: the switch looks like one virtual device per upstream port, Fabric Manager binds downstream modules. The win is utilization. Cloud nodes are sized for the p99 memory footprint; most of the time that DRAM sits idle. Pooling is how you stop buying it. The cost is a switch hop (~500–600 ns in public CMM-B and academic switch-path numbers) and a control plane.

Sharing. The same bytes, hardware-coherent, mapped by more than one host. CXL 3.0. This is the shared-memory cluster, not the stranded-capacity fix. It needs back-invalidate, a 3.x fabric, and software that knows it is not talking to a local NUMA node. Demos exist (UnifabriX has shown CXL 3.0 sharing; Astera's P-series claims pooling/sharing on a 2.0 controller with host help). General-purpose, multi-host coherent sharing in production AI racks is not 2026's volume design.

Tiering. A policy, not a topology. Software (Linux NUMA, memtier, LMCache for KV) or hardware (Intel Flat Memory Mode) decides that this cacheline belongs in local DDR and that one belongs in CXL. Samsung's KV-cache white paper on CMM-D behind a CXL 2.0 switch, on an 8× RTX PRO 6000 Blackwell box, is a tiering study: 1 TB of pooled CMM-D as the overflow tier for vLLM + LMCache. They are explicit that the Broadcom PCIe switch in that GPU server does not speak CXL, so the CXL switch takes a separate PCIe 5.0 x16 slot. That sentence is the 2026 GPU story in miniature. The GPU complex is still PCIe/NVLink/HBM. CXL is a sidecar.

Why AI servers care — and why this is not an HBM story

The memory wall in a 2026 training GPU is on-package. HBM4 and the CoWoS slot decide whether a Blackwell-class part ships with 192 GB or 288 GB at 8 TB/s. CXL cannot reach that interface. The PHY is the wrong width, the latency is the wrong number, and the GPU's memory controller talks to HBM PHYs on the interposer, not to a CXL.mem device in a PCIe slot.

The memory wall in a 2026 server is different. Three places spill.

CPU-side capacity next to the GPU. Recommendation models (DLRM) keep embedding tables in host DRAM that the CPU (or a GPU DMA) has to stream. Astera's published DLRM work with AMD EPYC 9005 and Leo claims a 70% recommendations-per-second lift from CXL expansion; a separate 5th Gen Xeon slide says +50% memory bandwidth and capacity. Those are vendor application notes. The Micron/Intel Xeon 6 paper is the independent-ish version of the same idea: eight Type-3 devices, +24% geomean. For inference TCO, a 24% bandwidth add on the host is not a new GPU. It is a cheaper way to keep the GPU fed.

KV-cache overflow. Long-context inference wants terabytes of KV that will not fit in HBM. The next tier is host DDR; the tier after that is CXL or NVMe. Samsung's CMM-D + LMCache paper is the primary-source version of "put the cold KV in a CXL pool." SK hynix has described an Inference Memory Tiering Expansion (IMTE) architecture in 2026 with a claimed 35.7% throughput gain — company testing, specific conditions, treat as analysis. The architectural claim is sound even if the percentage is marketing: CXL sits between DDR and SSD on the latency ladder (hundreds of nanoseconds versus tens of microseconds), so it is a real tier, not a rename of CXL.mem as "HBM for the rack."

Stranded DRAM in the fleet. Hyperscalers size nodes for the worst job. CXL 2.0 pooling is the TCO argument: put 512 GB of cheap, slower DRAM in a box, and give it to whichever node ran hot this hour. Google- and Meta-style papers on CXL (and the Microsoft/Columbia Octopus measurements circulating in 2026) keep landing on the same split: direct-attach expansion often pays; switch-based pods only pay if the topology is simple and the software actually returns memory. A 4,096-node PBR fabric is not required for that. A CMM-B with three hosts might be.

What CXL does not do in 2026 is replace NVLink for GPU scale-up, replace InfiniBand/Ethernet for scale-out, or let you build a GPU with no HBM. AI-chip startups chasing NVIDIA still live and die on package-local memory and a scale-up fabric. CXL is a CPU and memory-expander story that happens to sit in the same rack.

The hardware: controllers, modules, boxes, hosts

Memory modules: Samsung, SK hynix, Micron

Samsung's CMM-D is the Type-3 module the rest of the stack is measured against. CMM-D 1.0 was CXL 1.1 (2022); CMM-D 2.0 was CXL 2.0 (2023); Red Hat certified a CMM-D infrastructure in June 2024. The devices in the 2026 KV-cache paper are MD220 256 GB modules. CMM-B is the box: Xconn switch silicon, 4U, Fabric Manager, SLD pooling, up to 22 modules. Memcon 2024's earlier public KPI — 8 modules, 2 TB, 60 GB/s, 596 ns — is the number to remember for a switched pool. Direct CMM-D attach is faster than that; the switch is the extra hundred-plus nanoseconds.

SK hynix's first-generation CMM-DDR5 (CXL 2.0) went through customer qualification in 2025. A 256 GB CXL 3.2 second-generation sample appeared at HPE Discover in June 2026 in a Liqid pooled-memory server. Production timing is not a company 8-K. Micron's CZ120 (CXL 2.0, 2023) and CZ122 (128 GB E3.S) are the parts in the Xeon 6 bandwidth paper.

A 2026 industry wrinkle, reported by Korean trade press and not by the memory makers' IR decks: Samsung, SK hynix, and Micron have pulled back from shipping their own CXL controllers and are buying or sampling controllers from Montage (MXC) and Astera. Treat that as supply-chain reporting. The module you buy still has someone's DRAM and someone's controller; the controller brand is increasingly not the DRAM brand.

Controllers and cards: Astera Labs, Montage

Astera Labs' Leo is the production CXL 1.1/2.0 memory controller that the CPU vendors point to. The portfolio brief is specific: E-series for expansion (x8 and x16, 2-channel DDR5-5600, up to 2 TB, production), P-series for expansion plus pooling/sharing (x16, production), A-series A1000 add-in card with four DDR5-5600 RDIMM slots, 2 TB, pooling/sharing, production. COSMOS is the diagnostics and fabric-management software. Interop pages cover Xeon 6 and EPYC 9005, and 96/128 GB DDR5-4800/5600 from the three memory vendors.

Montage's MXC is the other merchant controller. CXL Type-3, pooling and sharing, a 3.1 part (M88MX6852) sampled in 2025 at 64 GT/s on x8 with dual-channel DDR5. If the DRAM vendors really did step back from in-house controllers, Montage and Astera are the remaining Type-3 PHY/controller vendors that matter.

Switches and fabrics: Xconn, UnifabriX, and everyone else

Xconn's XC50256 is the CXL 2.0 / PCIe 5.0 switch SoC in Samsung's CMM-B. The Consortium's Q2 2025 sharing webinar described it as 256 lanes, 2,048 GB/s aggregate, hybrid CXL/PCIe, in production. Marvell's acquisition of Xconn (widely reported; confirm against Marvell IR if you are writing a deal note) would make that switch a merchant-silicon product inside a larger connectivity company. For this guide the relevant fact is simpler: a CXL 2.0 switch chip exists, ships, and is how a pooling box is built.

UnifabriX is the system company on the fabric side of the Consortium membership. Smart Memory Node, Memory over Fabrics, MAX — pooling, sharing, and software-defined tiering, with CXL 2.0/3.0 demos going back to SC22 and a 2025–2026 pitch that also names UALink and ESUN/SUE. That last part is the tell. UnifabriX is building toward a memory fabric that may not stay CXL-only. Treat current products as CXL-attached memory nodes and pooling systems, not as a drop-in NVLink replacement.

Liqid, GigaIO, and a short list of composable-infrastructure vendors have been putting CXL Type-3 devices behind their own managers. They are the software and chassis layer on top of the same expanders.

Hosts: Intel, AMD, and the NVIDIA-shaped hole

Intel: 4th Gen Xeon (Sapphire Rapids) brought CXL 1.1; 5th Gen (Emerald Rapids) firmed up Type-3; Xeon 6 is the 2.0 host with Flat Memory Mode. The 6900P in the Micron paper exposes 96 PCIe 5.0 lanes and allows any four x16 links as CXL. More lanes on other SKUs, per the Hot Chips deck. Xeon 6+ Clearwater Forest (Computex 2026) is still CXL 2.0 on 96 PCIe 5.0 lanes — an 18A E-core density play, not a 3.x fabric play. GAAFET is how those transistors are built. It does not change the CXL generation.

AMD: EPYC 9004 (Genoa) had CXL 1.1 Type-3; EPYC 9005 (Turin) is the 2.0 host Astera validated for DLRM. Infinity Fabric remains the socket-to-socket coherent link. CXL is the I/O-side memory expander.

NVIDIA: Consortium-level engagement is real — the 4.0 announcement was delivered with a NVIDIA engineer as Consortium president — and Grace-class CPUs speak CXL as a CPU. The GPU scale-up path in 2026 is still NVLink and HBM. There is no public NVIDIA datasheet that puts CXL.mem on the path between two Blackwell GPUs. If a future Vera/Rubin CPU–GPU node uses CXL for host memory expansion, that is a CPU feature, not a replacement for NVLink. Do not read a Consortium press release as a GPU product.

Numbers that survive contact with a datasheet

Latency and bandwidth are where CXL marketing goes to die, so here are the measurements that have a method attached.

Local DDR5 on a modern Xeon/EPYC is roughly 80–130 ns idle, depending on whether you believe MLC, a paper's pointer-chaser, or Meta's ~130 ns idle figure. Under load, add tens of nanoseconds.

Direct Type-3 ASIC expanders. Melody (ASPLOS characterization of four vendor devices on Sapphire/Emerald Rapids) measured 214–394 ns and 18–52 GB/s. The fast ASICs cluster at 210–270 ns. FPGA expanders are slower (~375–400 ns). Hitchhiker's Guide (arXiv 2411.02814) agrees: ASIC CXL 200–300 ns local, FPGA ~400 ns, pooled/shared devices >500 ns.

Switched pools. Samsung CMM-B at Memcon 2024: 596 ns, 60 GB/s, 8 modules / 2 TB. Academic switch paths in the same literature sit at 490–600 ns. That is 4–6× local DDR, and still ~100× faster than a median 4K NVMe read.

Expansion bandwidth on a full CPU. Micron CZ122 × 8 on Xeon 6 6900P, Linux 6.9+ interleaving: +24% read-only, +39% mixed, +24% geomean on HPC/AI workloads, on top of 12 channels of DDR5-6400. This is the number to use when someone says CXL "doubles bandwidth." It doubled nothing. It added a useful fraction on a CPU that already had a lot of DDR.

HBM, for calibration. A single HBM3e 8-Hi stack is on the order of 1 TB/s at a few tens of nanoseconds on-package. Eight of them on CoWoS are the GPU's memory. CXL is not in that column of the table. Putting CXL and HBM on the same slide as "AI memory" is how you write vendor copy.

PCIe 5.0 x16 theoretical is ~64 GB/s each way. PCIe 6.0 x16 is ~128 GB/s. CXL 3.0's "256 GB/s aggregate raw" is that x16 at 64 GT/s, both directions, before encoding and protocol overhead. Real Type-3 devices in 2026 are almost all 5.0 x8 or x16. A 3.x x16 module is a 2026 sample, not a fleet part.

The honest 2026 picture

One useful heuristic: ask whether the device is Type 3, whether the link is 2.0 or 3.x, whether there is a switch, and whether the software is expansion, pooling, sharing, or tiering. Do not ask whether the server "supports CXL."

The bottom line

2026 is the year CXL Type-3 memory stopped being a Hot Chips slide and became a part you can put in a PCIe slot or an E3.S bay on a Xeon 6 or EPYC 9005.

The physics is old. A CPU that has filled its DDR channels still has PCIe lanes, and those lanes can carry cachelines instead of NVMe frames. Direct-attach expansion adds tens of percent of bandwidth and a terabyte-class of capacity at roughly 2× DDR latency. A CXL 2.0 pooling box adds a way to stop stranding that capacity across a few hosts, at roughly 5× DDR latency. Neither of those is HBM. HBM remains the GPU's working set on CoWoS. CXL is the next hop: KV-cache overflow, embedding tables, IMDB, and the TCO argument for not soldering 2 TB of DDR5 onto every node.

For anyone making decisions today, the split is clean. If the question is how to give a 2026 CPU more DRAM without waiting for the next DIMM generation, you are looking at a Type-3 card or E3.S module, CXL 2.0, and Linux that knows how to interleave. If the question is whether several servers can share a pool, you are looking at a CMM-B-class box and a fabric manager, still 2.0, still exclusive slices. If the question is whether CXL is the rack-scale fabric that replaces NVLink and Ethernet, the answer is no — not this year, and not on the hosts you can order. The 3.x and 4.0 papers are how that fabric would work. The shipping SKU is still an expander.

Frequently asked questions

What does CXL stand for?

Compute Express Link. An open interconnect standard maintained by the CXL Consortium. It runs cache-coherent memory and I/O protocols over a PCI Express physical layer.

Is CXL a type of memory, like HBM or DDR5?

No. The DRAM inside a Type-3 module is DDR5 (or, in older cards, DDR4). CXL is the protocol and the controller that make that DRAM appear in the CPU's address space. HBM is a stacked-DRAM package on the GPU interposer. They sit at opposite ends of the memory hierarchy.

What is the difference between CXL.io, CXL.cache, and CXL.mem?

CXL.io is the PCIe-like configuration and DMA channel. CXL.cache lets a device cache host memory. CXL.mem lets the host access device memory with load/store semantics. Type 3 — the expander — uses .io and .mem. Type 2 — the accelerator-with-memory — uses all three.

What is the difference between memory pooling, sharing, and tiering?

Pooling assigns exclusive slices of a CXL device to different hosts (CXL 2.0). Sharing maps the same coherent bytes to multiple hosts at once (CXL 3.0). Tiering is a policy that places hot lines in local DDR and cold lines in CXL, on one host. Expansion is one host adding Type-3 memory with no pool at all.

Does CXL replace HBM in AI GPUs?

No. 2026 training and large-inference GPUs still get their bandwidth from HBM on a CoWoS-class package. CXL attaches to the host CPU. It can hold overflow (KV cache, embeddings) that the GPU copies or that the CPU processes. It does not sit on the GPU's memory bus.

Which CPUs support CXL in 2026?

Volume hosts are Intel Xeon 6 (CXL 2.0, including Flat Memory Mode) and AMD EPYC 9005 (CXL 2.0). Intel 4th/5th Gen Xeon and AMD EPYC 9004 support earlier CXL 1.1 Type-3 expansion. NVIDIA Grace-class CPUs speak CXL as CPUs; NVIDIA GPUs scale up over NVLink, not CXL.mem.

How much slower is CXL than local DRAM?

Direct ASIC Type-3 devices measure about 210–270 ns versus ~80–130 ns for local DDR5, roughly 2–3×. A switch-based pool is ~500–600 ns in Samsung's CMM-B disclosure and in academic switch-path numbers. Both are orders of magnitude faster than NVMe.

Is CXL 3.0 or 4.0 shipping in servers?

The specifications are published (3.0 in 2022, 3.1 in 2023, 4.0 in November 2025). Memory vendors are sampling 3.2 modules. The hosts in volume in 2026 are CXL 2.0. A 3.x root complex in a shipping Xeon or EPYC is a next-generation question, not a current SKU.

Can multiple servers share one CXL memory pool today?

Yes, in the CXL 2.0 pooling sense: exclusive slices, a switch or MLD, a fabric manager, a handful of hosts. Samsung CMM-B is specified up to three hosts and 22 modules. Coherent multi-host sharing of the same bytes is a 3.x feature and a 2026 demo, not a fleet default.

Methodology

This guide is based on primary Consortium, CPU, memory, and controller disclosures available as of 19 August 2026: the CXL 3.0 white paper (Das Sharma / Agarwal; 64 GT/s on PCIe 6.0, 256 GB/s raw x16 aggregate, pooling vs sharing, PBR fabrics to 4,096 nodes, GFAM, enhanced coherency and back-invalidate); the CXL 3.1 white paper (GIM, PBR fabric-manager API, CXL-TSP confidential compute, 34-bit metadata, RAS); the CXL 4.0 specification release (18 November 2025; 128 GT/s on PCIe 7.0, bundled ports, native x2, four retimers, backward compatible to 1.0) and 4.0 white paper; Intel Hot Chips 2023 Xeon 6 / Granite Rapids public architecture slides (CXL 2.0, Flat Memory Mode, up to 136 lanes PCIe 5.0/CXL 2.0); Micron and Intel, "Optimizing System Memory Bandwidth with Micron CXL Memory Expansion Modules on Intel Xeon 6 Processors" (arXiv 2412.12491: eight CZ122 128 GB E3.S devices, +24% / +39% / +24% geomean on a 6900P); Samsung CMM-B white paper (4U, Xconn switch, up to 22× E3.S, 5.6 TB, three hosts, SLD pooling, FMAPI) and Samsung's KV-cache offload white paper (MD220 256 GB × 4 = 1 TB behind a CXL 2.0 switch on an 8× RTX PRO 6000 Blackwell server; explicit note that the GPU-side Broadcom PCIe switch does not speak CXL); Samsung newsroom Red Hat CMM-D certification (25 June 2024); Astera Labs Leo product page and portfolio brief (E-series expansion, P-series pooling/sharing, A1000 4× RDIMM / 2 TB add-in card, CXL 1.1/2.0, production); UnifabriX Consortium member spotlight and product pages. Melody (ASPLOS) and Hitchhiker's Guide (arXiv 2411.02814) supply independent latency/bandwidth ranges for Type-3 ASICs versus FPGAs versus pooled devices. Samsung CMM-D 3.0 / CXL 3.2 mass-production timing, SK hynix 256 GB CMM-DDR5 sampling at HPE Discover 2026, memory-vendor controller outsourcing, and SK hynix IMTE +35.7% are trade-press or vendor-test claims and are labeled as such. NVIDIA GPU scale-up is taken from NVIDIA's own NVLink/HBM product documentation, not from CXL Consortium materials. Retimers, lane counts, and theoretical PCIe 5.0/6.0/7.0 bandwidths are the standard encoding math used across the CXL and PCIe literature.