SiC and GaN Power Electronics: A Full Guide to the Chips That Feed AI Racks

Silicon carbide and gallium nitride are not a new way to generate electricity, and they are not a cooling loop. They are the switches that turn facility AC — or, on the 2027 slide, 800 volts of DC — into the voltages an AI rack can actually use. The product the operator buys is still a power supply unit, a bus converter, a hot-swap board, a battery backup unit, or a drive for a coolant distribution unit. The thing that changed is the semiconductor inside those boxes: a silicon MOSFET where cost and low voltage still win, a silicon carbide MOSFET or JFET where blocking voltage and heat win, a gallium nitride HEMT where switching frequency and density win.

That split exists because the alternative ran out of copper and heat. For twenty years, server power was a 12-volt, then a 48- or 54-volt, problem solved with silicon MOSFETs, a totem-pole or Vienna power-factor-correction stage, an LLC isolator, and a swarm of point-of-load bucks. At 10 kW a rack, that stack is boring and cheap. At 100 kW it is a copper busbar with a cooling problem. At a megawatt it is a physics argument NVIDIA has already named: 800 VDC, starting in 2027 with Kyber-class systems, not as a 2026 bill of materials.

What changed in 2026 is not that wide-bandgap devices were invented. SiC MOSFETs have been in EV inverters and solar inverters for a decade; GaN has been in phone chargers and 48-volt bus converters for several years. It is that AI racks crossed the power density where silicon's switching loss, conduction loss, and thermal resistance stop fitting in a 1U PSU, that every serious vendor published an 800-volt-class reference design or qualification, and that the 2026 volume path is still a 50-volt bus fed by 5.5–12 kW CRPS shelves. The useful question is which of those devices is in a shipping PSU, which is in a sidecar evaluation board, and which is still a GTC demo.

Key takeaways

• SiC and GaN are conversion, not generation and not heat removal. A small modular reactor is how you might make the megawatts. Liquid cooling is how you take the heat back out of the GPU and the PSU. Wide-bandgap switches sit in between: they decide how many watts of that electricity become useful current at 50 V, 12 V, or 0.8 V, and how many become PSU heat the CDU then has to pump away. Backside power delivery is a third, unrelated conversation — millivolt grids on a GAAFET die, not kilovolt grids in a rack.
• Silicon did not disappear. It ran out of room at the high-voltage, hard-switching sockets. Above about 1 kV, you cannot put a silicon MOSFET or a 650 V GaN HEMT in the socket; 1200 V SiC is the default. Around 600–650 V, silicon, SiC, and GaN compete. Below about 80–100 V, SiC is usually out and the fight is silicon versus GaN. Infineon's own system architects say there is no universal winner, only a right place for each, and that scoring them on device price alone is the worst way to design a 12 kW PSU.
• Voltage, switching frequency, and thermal conductivity are three different bills. SiC's ~3.26 eV bandgap and high critical field let a thinner drift region block 650–3300 V with lower on-resistance; its ~370–490 W/m·K thermal conductivity (4H-SiC) is why it survives hard switching and hot-swap. GaN's ~3.4 eV bandgap and ~1,700 cm²/V·s electron mobility (ST's own GaN numbers) give low output capacitance and almost no reverse-recovery charge, which is why it switches at hundreds of kilohertz to 1 MHz and shrinks magnetics. Silicon still wins the cheapest synchronous rectifier.
• 2026 volume racks are 50-volt, not 800-volt. NVIDIA's DGX GB200 rack user guide puts NVL72 at approximately 120 kW, with power shelves converting AC to a nominal 50–51 V DC bus through six air-cooled 5.5 kW PSUs per shelf, eight shelves, N+N redundancy. That is a CRPS-class, 48/54 V world with SiC in the PFC and GaN in the high-frequency stages — not an 800 VDC hall. NVIDIA's 800 VDC architecture is dated to 1 MW IT racks and Kyber, "starting in 2027."
• The 2026 vendor picture is reference designs, qualifications, and MGX slides. Infineon's 2 June 2026 pair is an 18 kW three-phase 50 V PSU reference (650 V CoolSiC + 80 V CoolGaN, 97.5% peak) and a 30 kW T-Type PFC evaluation board for 800 VDC or ±400 VDC sidecars (650 V CoolGaN bidirectional + 1200 V CoolSiC, >99% peak). Wolfspeed's 6 August 2026 LITEON deal is a SiC MOSFET qualification into 800 VDC sidecar and compute-rack PSU platforms, on 200 mm wafers. Navitas, ST, and EPC have 800-to-50/12/6 V boards at 6–12 kW and 96.5–98.5% — evaluated, shown at APEC/GTC/OCP, not a SKU you can assume is in a 2026 training rack.
• Efficiency at the PSU is a token-cost problem, not a green slogan. Every percent you lose in conversion is heat the CDU must remove and electricity you already paid for at the meter. That is the same bill as inference-chip TCO: joules per token, not TFLOPS on a slide. Lawrence Berkeley's 2025 update, cited by DOE, puts U.S. data centers at 11.8% of national electricity by 2030 in the reference case (9.5–15.3% across scenarios). Conversion loss is a small slice of that; it is also the slice the power-semiconductor vendors can actually move this decade.

SiC and GaN at a glance

What SiC and GaN actually are

Start with the thing they are not. They are not SMRs. A reactor makes megawatts at 13.8 kV or whatever the interconnect is; these transistors do not. They are not direct-to-chip liquid cooling. A cold plate removes heat after the GPU and the PSU have already turned watts into waste. They are not backside power. PowerVia moves a millivolt-class grid to the back of a logic die so HBM and signal metals can keep their tracks. A CoolSiC MOSFET in a 1200 V PFC is a different object, in a different package, on a different voltage, bought by a different team.

A power transistor is a switch. On, it should look like a short. Off, it should look like an open that can stand the bus voltage. Every time it changes state, it dissipates energy in the overlap of voltage and current, and the magnetics around it have to be sized for the frequency you picked. Silicon MOSFETs and IGBTs have done this job since the 1980s. Their limit is the material: a 1.12 eV bandgap, a critical field around 0.3 MV/cm, and a drift region that has to be thick — hence resistive — to block hundreds of volts.

SiC and GaN are wide-bandgap. 4H silicon carbide is about 3.26 eV; gallium nitride is about 3.4 eV (ST cites 3.4 eV and 1,700 cm²/V·s mobility for the GaN it puts in 800 V LLC stages). The higher critical field means a much thinner drift region for the same blocking voltage, which means lower on-resistance per area, which means less conduction loss or a smaller die. GaN's two-dimensional electron gas in a HEMT adds very low output charge and essentially zero reverse-recovery, which is why it likes 500 kHz–1 MHz LLC and ISOP converters. SiC's thermal conductivity is the other half of the pitch: you can dump hard-switching loss into a package that still has a path to the heatsink. GaN-on-silicon, the commercial power-GaN workhorse, does not get SiC's heat spreading; it gets frequency and size.

IEEE Spectrum's long-running map of the market is still the cleanest public split: GaN dominates below roughly 400 V, SiC has the edge at 800 V and above, and 400–1,000 V is the contested belt. Infineon's server-PSU architects draw the same map with sockets instead of volts. In a three-phase PSU the PFC rectifying bridge is now typically 1200 V SiC, because you cannot put silicon or GaN in that socket. Around 600–650 V all three compete. At 80 V or 40 V, SiC is out and it is silicon versus GaN on the synchronous rectifier. A 12 kW PSU, they note, might parallel 96 devices across those groups. GaN's job in that sentence is to cut the paralleled count.

Why silicon MOSFETs ran out of room

The congestion is not a slogan. It is current, frequency, and a 1U hole.

Current. Power is voltage times current. A 120 kW rack at 12 V is 10,000 A. At 48–54 V it is about 2,200–2,500 A — still a busbar, still a connector problem, but a busbar you can actually build, which is why GB200 NVL72 distributes a nominal 50 V. At 800 V the same 120 kW is 150 A; a 1 MW rack is 1,250 A instead of more than 18,000 A at 54 V. NVIDIA's 800 VDC architecture write-up is explicit: convert 13.8 kV AC toward 800 VDC at the perimeter, cut conversion stages, cut copper, claim up to 5% end-to-end efficiency versus today's 54 V path, and target 1 MW IT racks from 2027. That is a facility argument. The device argument is that the transistors which make 800 VDC real have to block 650–1200 V and switch cleanly at the frequencies that keep the magnetics inside a sidecar or a 1U.

Frequency and magnetics. Transformer and inductor volume falls as frequency rises, until core loss, copper AC loss, and EMI stop you. Silicon hard-switched PFC historically lived at tens of kilohertz. SiC totem-pole PFC lives at higher tens to low hundreds. GaN LLC and ISOP designs in the 2025–2026 AI boards are at 650 kHz–1 MHz: ST's 12 kW 800-to-50 V LLC at 1 MHz, Navitas's 10 kW 800-to-50 V platform at 1 MHz, EPC's 6 kW 800-to-12.5 V ISOP at 1 MHz. That is how you quote 2,000+ W/in³ on a power delivery board. It is also why the magnetics, the gate drive, and the layout became the product, not just the FET.

Thermal and form factor. A CRPS or ORv3 shelf is a specified hole. Infineon's 18 kW three-phase reference is 104 × 710 × 40 mm and 100 W/in³, with a −5 °C to 45 °C ambient envelope and a 20 ms hold-up for GPU EDPP peaks to 180%. You cannot get there by paralleling more silicon in the same box without the box becoming a heater the rack cannot air-cool. Wide-bandgap is how the loss moves out of the switch so the remaining heat is small enough for the existing liquid-cooling plant — or, in the 5.5 kW GB200 shelves, for air on the PSU itself.

The 48 V generation was the preview. Open Compute and the 48/54 V rack already forced a first wide-bandgap wave: GaN and SiC in 3 kW, then 5.5 kW, then 8.5–12 kW CRPS units through 2023–2025. Navitas's own timeline is the public one: 3.2 kW CRPS in August 2023, 4.5 kW at 137 W/in³, 8.5 kW GaN+SiC at 98% for OCP ORv3 in November 2024, a 12 kW unit shown at Computex in May 2025, then the 10 kW 800-to-50 V GaN platform in February 2026. That is a density ladder, not a material religion. Silicon stayed in the sockets where it was cheaper.

Voltage, switching frequency, thermal

Three benefits get sold as one. They do not pay on the same schedule.

Voltage class. Blocking voltage is the first filter. 1200 V SiC owns three-phase PFC bridges and 800 V hot-swap (you want headroom above an 800 V bus). 650 V is the melee: Infineon's 18 kW PSU uses 650 V CoolSiC in the PFC and 80 V CoolGaN on the low side; the 30 kW T-Type board uses 650 V CoolGaN bidirectional switches in the back-to-back path and 1200 V CoolSiC in the high-voltage stage. GaN at 650–700 V (ST's PowerGaN, Infineon's CoolGaN) is real in 2026. GaN at 1200 V is still the "coming" slide IEEE Spectrum was already hedging in 2024–2025. Do not write a 1200 V GaN PFC into a 2026 BOM because a conference abstract exists.

Switching frequency. This is GaN's bill. The 2025–2026 800 V boards — ST's 12 kW LLC, Navitas's 10 kW brick, EPC's 6 kW ISOP — all quote ~1 MHz and 2,000+ W/in³. Infineon's MGX language is GaN bus converters "at switching frequencies close to 1 MHz." SiC can switch faster than silicon; it is not why you pick 1 MHz. Numbered density claims live in the vendor section below.

Thermal. This is SiC's bill, and the reason hot-swap and hard-switched PFC do not automatically go GaN. Wolfspeed's January 2026 TOLT (TO-leaded, top-side cooled) Gen 4 650 V MOSFETs exist because the package, not the epitaxy, was the density limiter in a PSU. Infineon sells .XT diffusion-solder die attach as up to 25% lower RthJC. ST puts 1200 V SiC, not GaN, in the 800 V hot-swap path, and Infineon puts a SiC JFET plus control ICs in the same socket on native 800 V server boards. GaN-on-silicon still dumps heat through a silicon substrate and a small package. That is fine at 1 MHz in an LLC that is already soft-switched. It is a different conversation in a fault that has to ride an 800 V bus until a breaker opens.

A short mapping, because the slides will not provide one.

Where they sit in an AI hall

Follow the current.

Facility and UPS. Medium-voltage AC arrives at a substation. A double-conversion UPS or a rotary/battery hybrid sits in front of the hall. SiC in that inverter is a 2020s product story, not an AI exclusive: lower loss at partial load, smaller magnetics, less cooling in the electrical room. Battery backup units at the rack (ORv3-style) are the AI-specific cousin — Wolfspeed's LITEON release names PSUs and BBUs as the 800 VDC applications. This is still conversion. It is not nuclear and it is not a reason to skip a utility interconnect.

Power shelf / CRPS / sidecar. On a 2026 GB200-class rack the shelf takes three-phase AC and emits ~50 V DC onto a busbar. NVIDIA's user guide: six 5.5 kW air-cooled PSUs per shelf, eight shelves, 33 kW per shelf input, N+N, ~120 kW rack. Infineon's 18 kW three-phase reference is the density next step on that 50 V architecture; the 30 kW T-Type PFC board is the sidecar for 800 VDC or ±400 VDC, "available for evaluation soon" as of 2 June 2026. Sidecar means the conversion can live in an adjacent cabinet so the compute rack is mostly GPUs, HBM, and cold plates. It is how you retrofit 800 V without waiting for a greenfield 800 VDC factory.

Intermediate bus converter and power delivery board. 50 V (or 48 V, or 12 V) still has to become the GPU core, the HBM rails, and the NIC. Traditionally that is a two-stage story: IBC then point-of-load. The 2026 800 V demos try to skip a stage. Navitas's March 2026 GTC board is 800 V to 6 V in one stage, "eliminating the traditional 48 V IBC." ST's March 2026 pair is 800-to-12 V at 6 kW (97.5% peak, 2,500 W/in³) and 800-to-6 V at 20 kW (96.5% peak). EPC's ISOP 800-to-12.5 V claims 1–2% system efficiency for skipping 48 V. Infineon, on MGX, says it converts 800 V to 50 V, 12 V, "or even down to 6 V." Three output voltages are not three winners. They are three server-board conventions that will coexist, which is ST's own March 2026 line: 50 V, 12 V, and 6 V buses will all be in AI data centers depending on GPU generation, height, and thermal envelope.

Hot-swap and protection. An 800 V board you can plug in live is a safety product before it is a converter. ST's architecture splits the problem: 1200 V SiC plus isolated BCD controllers for hot-swap, 650 V GaN stacked half-bridge for the LLC. Infineon's MGX note matches: SiC JFET plus control ICs for protection and hot-swap on native 800 V server boards. This is the unglamorous reason 800 VDC is a 2027 architecture. The FET was not the long pole. The connector, the isolation, the arc-flash study, and the service procedure were.

CDU. A coolant distribution unit is a pump and a heat exchanger. Its drive can use SiC. That does not make the CDU a SiC story; it exists because the GPU is liquid-cooled.

48/54 V now, 800 VDC later

Two architectures are being sold as one replacement. They are a sequence.

Now (shipping). 48 V or 54 V rack distribution, CRPS or ORv3 shelves, AC into the row. GB200 NVL72 is the existence proof at ~120 kW. The wide-bandgap content is inside the PSU: SiC PFC, GaN or hybrid isolated DC-DC, silicon (and rising GaN) on the output. Power density is 80–140 W/in³ in the best public CRPS numbers from 2024–2025. Hold-up capacitors and EDPP transients (Infineon: 180% GPU peaks, 20 ms) are the AI-specific requirement silicon-era PSUs did not size for.

Bridge (design wins, 2026–2027). Hybrid: keep the hall AC, put a three-phase 800 VDC or ±400 VDC sidecar next to the rack, feed native 800 V boards or a late-stage converter. Infineon's 30 kW PFC board is aimed here. Wolfspeed + LITEON (6 August 2026) is a SiC qualification into "800 VDC power sidecar and compute rack PSU platforms" for hyperscale customers — a design-in, not a statement that those platforms are the 2026 installed base. NVIDIA's own MGX language, which Infineon joined on 29 May 2026, is an upgrade path that "helps existing AI infrastructure" without waiting for a full 800 VDC factory.

Later (NVIDIA's dated claim). Convert MV AC to 800 VDC once, at the perimeter, with industrial rectifiers or a solid-state transformer. Distribute 800 VDC down the hall. One high-ratio converter at the tray. NVIDIA: full-scale 800 VDC production coinciding with Kyber in 2027, up to 5% end-to-end efficiency, up to 30% TCO in the blog's own framing, 1 MW IT racks. Treat the TCO figure as NVIDIA's. Treat the date as a product-roadmap date, not as a utility interconnection date. Most 2026 concrete is still being poured for 50 V racks that need CDUs, not for 800 VDC switchgear.

±400 V is a topology fork that reuses 650 V devices more comfortably; Infineon's 30 kW board and ST both say they can serve it. It is not a different material.

Five vendors, five different bets

Infineon wants the whole chain and all three materials. The 2 June 2026 technology note numbers the 18 kW and 30 kW boards; the 29 May 2026 MGX release is the architecture claim (GaN near 1 MHz, SiC JFET hot-swap, 800-to-50/12/6 V). "Grid to core" is a portfolio. Ask which SKU is in the rack.

Wolfspeed sells SiC MOSFETs, not PSUs. The 6 August 2026 LITEON partnership qualifies those MOSFETs into 800 VDC sidecar and compute-rack PSU platforms on 200 mm wafers. The January 2026 TOLT family is the 650 V package story. A qualification is not a wafer-output guarantee; Wolfspeed's July 2026 patent suit against Navitas is a reminder that this supply chain is small.

Navitas put GaNFast and GeneSiC on NVIDIA's 800 V collaboration first (21 May 2025). The February 2026 10 kW all-GaN 800-to-50 V brick (98.5% peak, 1 MHz) and the March 2026 800-to-6 V GTC board are evaluation platforms, debuted at APEC/GTC. GeneSiC 3.3 kV SST language is a roadmap object, not a 2026 hall drawing.

EPC does not make 650 V GaN. It stacks 150 V and 40 V eGaN FETs in ISOP so 800 V can fall to 12.5 V. The 1 June 2026 EPC91123 note is the primary source: 6 kW, 98.2/97%, 8 mm, MGX. Eight 750 W bricks versus one 16:1 650 V transformer is a real topology argument. It is also an eval board.

ST showed NVIDIA a smartphone-sized 12 kW 800-to-50 V LLC at OCP 2025 (newsroom). The ST blog is the technical source: 1200 V SiC hot-swap, 650 V GaN stacked half-bridge, split transformers. March 2026 added 800-to-12 V (6 kW, 97.5%) and 800-to-6 V (20 kW, 96.5%). "NVIDIA validated" a proof of concept is not exclusive Kyber silicon.

Others sit in the same drawing — onsemi, ROHM, Texas Instruments, Analog Devices on the control side, Delta/Liteon/Flex/Bel on the PSU metal — and they matter. The five above are the ones this brief named, and they are enough to show the pattern: nobody credible is "SiC versus GaN." Everybody credible is "which socket."

What still breaks

800 V eval boards are real. That does not make 800 VDC boring.

Substrate and wafer supply. SiC starts as a boule, not a 300 mm silicon wafer. 200 mm is the 2026 manufacturing story Wolfspeed is selling; yield, defect density, and epitaxy thickness for 1200 V devices are still the cost. GaN power is mostly GaN-on-silicon, which is why it scaled through chargers, and why 1200 V GaN is hard. Anyone quoting SiC at silicon cost is selling a 2028+ learning curve as a 2026 PO.

Magnetics and packaging, not the FET. 1 MHz at 10 kW is a transformer, a planar winding, an EMI filter, and a gate-drive layout. Infineon's 18 kW note spends as many words on planar magnetics and an integrated energy buffer (50% less capacitor volume, 20 ms hold-up) as on CoolSiC. ST split one transformer into two sets of four to spread flux and heat. EPC's ISOP pitch is smaller transformers. The FET without that work is a datasheet.

Hot-swap, isolation, arc flash. 800 VDC in a serviceable rack is a standards problem. Creepage, clearance, 10 kV isolation occupying transformer volume (ST's own constraint), connector derating, and a procedure a technician can survive are why "the GaN board is 8 mm tall" is not the same as "the rack is ready."

Dynamic load. AI is not a telecom rectifier's 80% load line. GPU EDPP and all-reduce spikes are why Infineon sized 180% peaks and a 20 ms buffer, and why NVIDIA's 800 VDC ecosystem posts keep pairing HVDC with energy storage. A PSU that is 99% at DC load and sags on a 100 µs transient is a failed training job.

Control and sensing. 1 MHz converters need fast timers (ST: STM32G4 at <200 ps) and isolated sensors that survive SiC/GaN dV/dt (Infineon: XENSIV TLE4978). Unsexy, on the critical path.

The 2026/2027 clock. NVIDIA dated native 800 VDC to 2027 Kyber. 2026 is 50 V racks at 100–150 kW, liquid-cooled, with hybrid PSUs. Shipping a 30 kW PFC evaluation board in June 2026 is exactly on that clock. Writing as if the GB200 hall you are fitting this quarter is 800 VDC is how you order the wrong busway.

It does not shrink the GPU bill. Inference TCO is still the accelerator, the HBM, and utilization. A 1–5% conversion win is real hall-scale money, not a substitute for a fuller rack.

A realistic timeline

One useful heuristic: ask what voltage the busbar in the rack actually is, which socket the FET sits in, and whether the number you were quoted is a PSU you can order or a reference design. Do not ask whether the vendor "supports SiC and GaN."

The bottom line

2026 is the year wide-bandgap power electronics became the default answer for the next AI rack — and the year the rack you can actually buy is still a 50-volt, 120 kW, liquid-cooled cabinet with silicon in it.

The physics is old. At 100 kW and above, 12 V is impossible and 54 V is a copper-and-loss compromise; 800 VDC is how you cut current, stages, and some percentage of the electricity bill, and NVIDIA has dated the native version of that to 2027. SiC takes the high-voltage, hard-switched, hot sockets. GaN takes the high-frequency, small-magnetics sockets. Silicon keeps the cheap ones. Infineon, ST, Navitas, EPC, and Wolfspeed are all, in different combinations, selling that split: 18 and 30 kW references, 6–12 kW 800-volt boards, a LITEON qualification, MGX logos. Those are real. They are not a 2026 800 VDC hall, and they are not a substitute for the reactors or the CDUs the hall also needs.

For anyone making decisions today, the split is clean. If the question is what is inside a GB200-class power shelf, you are looking at hybrid CRPS-class conversion onto ~50 V, with SiC and GaN already in the better units. If the question is what to design for a 2027 800 V tray, you are looking at 1200 V SiC protection, 650 V GaN (or stacked low-voltage GaN) isolation, and a fight among 50 V, 12 V, and 6 V outputs. If the question is whether a vendor's "SiC/GaN for AI" story is real, ask which socket, which voltage, which numbered efficiency and density, the name of the PSU OEM, and whether the thing is a shipping shelf or an evaluation board. The bandgap in the press release will not answer it.

Frequently asked questions

What are SiC and GaN power electronics?

Silicon carbide MOSFETs/JFETs and gallium nitride HEMTs used as high-efficiency switches in power converters. In AI data centers they sit in PSUs, bus converters, hot-swap circuits, and backup units — not in the GPU and not in the reactor.

Why can't silicon MOSFETs feed 100 kW+ AI racks alone?

They can, at a cost in loss, paralleled devices, magnetics volume, and heat. At 120 kW the rack has already left 12 V for ~50 V. Pushing density into 1U, three-phase, and eventually 800 VDC makes silicon's switching loss and on-resistance at high voltage the limiter. Hybrid designs keep silicon where it is cheap.

Is SiC better than GaN?

Not as a single score. SiC wins blocking voltage, thermal conductivity, and hard-switched / hot-swap sockets (typically 650–3300 V). GaN wins switching frequency and density in isolated DC-DC and bus converters (typically ≤650 V, or stacked lower-voltage parts). IEEE Spectrum and Infineon's own PSU architects both draw it that way.

Are 2026 AI racks already on 800 VDC?

No. NVIDIA's DGX GB200 documentation describes ~120 kW racks with AC-to-~50 V power shelves. NVIDIA's 800 VDC architecture is aimed at 1 MW-class IT racks and Kyber, starting in 2027. 2026 800 V work is reference designs, eval boards, and OEM qualifications.

Where do these devices sit relative to liquid cooling and SMRs?

SMRs (and other generation) make the energy. SiC/GaN convert it. Liquid cooling removes the heat from GPUs and from whatever the converters still lose. A more efficient PSU slightly shrinks the cooling bill; it does not replace a CDU.

Is this the same as backside power delivery?

No. Backside power is an on-die wiring scheme for GAAFET logic. SiC/GaN are discrete (or module) power devices at tens to thousands of volts.

Who actually makes the parts?

Infineon (Si/SiC/GaN, 18/30 kW refs, MGX), Wolfspeed (SiC MOSFETs, LITEON 800 VDC qualification, 200 mm), Navitas (GaNFast + GeneSiC platforms), EPC (low-voltage eGaN ISOP boards), ST (SiC hot-swap + GaN LLC, NVIDIA-shown 12 kW board). PSU OEMs such as LITEON still box them.

Will GaN replace SiC at 1200 V?

Not in 2026 volume. 650–700 V GaN is in production for these converters. 1200 V GaN remains a "when it industrializes" item. Hot-swap and three-phase PFC at 1200 V are SiC sockets on every primary source cited here.

Does a 98% PSU solve data-center electricity growth?

No. DOE, citing LBNL's 2025 update, puts U.S. data centers around 11.8% of national electricity by 2030 in the reference case. Conversion efficiency is a 1–5% lever on a bill dominated by compute utilization, HBM and accelerator draw, and cooling. It is worth taking. It is not the generation problem.

Methodology

This guide is based on primary vendor, operator, and government disclosures available as of 23 August 2026. NVIDIA's DGX GB Rack Scale Systems user guide (rack power approximately 120 kW; power shelves convert AC to nominal 50–51 V DC; six air-cooled 5.5 kW PSUs in eight shelves, N+N, 33 kW per shelf) is the 2026 volume-rack primary source. NVIDIA's technical blog "NVIDIA 800 VDC Architecture Will Power the Next Generation of AI Factories" and the companion 800 VDC product page date native 800 VDC and 1 MW IT racks to 2027 / Kyber, claim up to 5% end-to-end efficiency versus 54 V paths, and describe MV AC conversion at the perimeter. Infineon's 2 June 2026 technology news "Infineon pushes AI data center power supply units (PSU) to 30 kW…" (18 kW three-phase 50 V PSU reference: 650 V CoolSiC, 80 V CoolGaN, 5-level ANPC, 97.5% peak, 100 W/in³, 104 × 710 × 40 mm, 20 ms hold-up, 180% EDPP; 30 kW T-Type PFC eval: 650 V CoolGaN bidirectional + 1200 V CoolSiC, >99% peak, iTHD <5% above 30% load, PF >0.99; both "available for evaluation soon") and 29 May 2026 MGX press release (GaN bus converters near 1 MHz, SiC JFET hot-swap, 800-to-50/12/6 V) are the Infineon primaries, with the Si/SiC/GaN PSU white paper as the hybrid-architecture background. Wolfspeed's 6 August 2026 LITEON release (SiC MOSFET qualification into 800 VDC sidecar and compute-rack PSU platforms; 200 mm SiC) and 29 January 2026 TOLT/Gen 4 650 V announcement are the SiC-device primaries. Navitas's 9 February 2026 10 kW 800-to-50 V GaN platform (98.5% peak, 98.1% full load, 1 MHz, 2.1 kW/in³, 61 × 116 × 11 mm, customer evaluation, APEC debut), 16 March 2026 800-to-6 V GTC board, and 21 May 2025 NVIDIA 800 V collaboration (3.2 / 4.5 / 8.5 / 12 kW CRPS ladder) are the Navitas primaries. ST's 13 October 2025 newsroom item (12 kW GaN LLC, 800 V, 1 MHz, >98%, >2,600 W/in³ at 50 V, OCP 2025) and the ST blog "800 V HVDC for AI data centers" (1200 V SiC hot-swap, 650 V GaN stacked half-bridge, March 2026 6 kW 800-to-12 V at 97.5% / 2,500 W/in³ and 20 kW 800-to-6 V at 96.5%, June 2026 MGX) are the ST primaries. EPC's 1 June 2026 EPC91123 note (6 kW, 800-to-12.5 V ISOP, 98.2% peak / 97% full load, EPC2305 150 V + EPC2366 40 V, 104 × 47 × 8 mm, MGX) is the EPC primary. Material physics: ST blog GaN 3.4 eV and 1,700 cm²/V·s; IEEE Spectrum's GaN-below-~400 V / SiC-at-800 V+ market split. Demand context: DOE "Powering America's AI Future" hub citing LBNL United States Data Center Energy Usage Report: 2025 Update (OSTI 3374245, 18 June 2026) — 11.8% of U.S. electricity by 2030 reference (9.5–15.3%; 649 TWh reference). Infineon server-PSU architect comments on socket-by-socket Si/SiC/GaN (The Data Center Engineer interview with Sam Abdel-Rahman) are used only as color consistent with Infineon's own numbered releases. Unofficial BOM prices, unsourced "GaN wins AI" scorecards, and any claim that 2026 GB200 halls run 800 VDC are omitted or labeled. Generation (SMR) and heat removal (CDU/cold plate) are cross-referenced, not re-derived.