SOCAMM: A Full Guide to Detachable LPDDR5X When Soldered Memory Hits the Wall

Soldered LPDDR5X solved Grace-class bandwidth and power. It also locked capacity to the motherboard. When a package fails, or when you need more DRAM next quarter, the board leaves with it.

The detachable answer on NVIDIA's Vera path is SOCAMM, Small Outline Compression Attached Memory Module: LPDDR5X in a field-replaceable compression socket instead of a permanent BGA. Official Vera numbers put the subsystem at up to 1.2 TB/s of bandwidth and up to 1.5 TB of capacity. JEDEC published JESD328 for SOCAMM2 in June 2026, moving the form factor from a vendor-first module into a named standard.

This guide covers what SOCAMM and SOCAMM2 are, how Vera uses them, what the mid-2026 capacity cut actually changed, how the column differs from DDR5 RDIMM/MRDIMM, HBM, GDDR7, and CXL, and where the honest limits sit as of September 2026. Host DDR5 muxing lives in the MRDIMM guide. Near-package GPU memory is HBM. Board graphics DRAM is GDDR7. Host expanders are CXL. Do not merge those columns on a BOM.

Key Takeaways

• SOCAMM (Small Outline Compression Attached Memory Module) puts LPDDR5X on detachable, field-replaceable modules instead of soldering packages to the motherboard (NVIDIA Vera product page).
• NVIDIA Vera claims up to 1.2 TB/s LPDDR5X bandwidth and up to 1.5 TB capacity via SOCAMM, framed as roughly 2x bandwidth at half the memory power versus traditional CPU memory, and 3x bandwidth per core versus leading x86 CPUs with DDR5 (Vera datasheet).
• JEDEC published JESD328 (SOCAMM2 Common Standard) in June 2026, with Raw Card A annex JESD328-J0-RCA in May 2026; SOCAMM2 is the standardized path after NVIDIA's earlier vendor-first SOCAMM generation.
• As of June 2026 industry reporting, default SOCAMM2 shipping capacity moved from 192 GB modules to 96 GB modules (four LPDDR5X packages per module; stack height cut) because of LPDDR supply pressure, while each Vera CPU still takes eight modules.
• Honest limits: SOCAMM is not HBM, not DDR5 MRDIMM, and not a universal x86 DIMM. "Up to 1.5 TB" assumes 8×192 GB; many racks will ship closer to 8×96 GB = 768 GB per CPU until supply recovers.

SOCAMM at a glance

Naming: SOCAMM vs SOCAMM2

Start with the labels. Vendors and JEDEC do not use them identically.

SOCAMM is the category name: Small Outline Compression Attached Memory Module. NVIDIA used that language on Vera and in the Rubin platform write-up for detachable LPDDR5X modules that improve serviceability and fault isolation versus soldered packages.

SOCAMM2 is the JEDEC-standard edition. JESD328 (LPDDR5/5X SOCAMM2 Common Standard) published in June 2026. The Raw Card A annex JESD328-J0-RCA published in May 2026 and defines design details for x32 LPDDR5/5X DRAM up to four ranks on SOCAMM2. JEDEC's own abstract says "SOCAMM" is general language and "SOCAMM2" is the standard version.

Treat first-generation NVIDIA SOCAMM as the vendor-first module that proved the idea, and SOCAMM2 as the interoperable standard path. Secondary reporting in September 2025 already described NVIDIA shifting emphasis to SOCAMM2 and faster LPDDR5X rates. For RFPs in September 2026, ask for JESD328 SOCAMM2 compliance, not just the marketing acronym.

Why detachable LPDDR beats soldered LPDDR on AI CPUs

Grace-era designs showed the bandwidth and power case for LPDDR5X next to an Arm CPU. Soldered packages also showed the operations cost: capacity is fixed at board build, and a bad package is a board event.

NVIDIA's Vera page states the tradeoff directly. Traditional DDR5 forces a compromise among bandwidth, efficiency, and serviceability. Vera pairs LPDDR5X with SOCAMM so the modules stay detachable, field-replaceable, and capacity-upgradable while keeping low-power DRAM economics.

That matters for AI factory uptime language as much as for peak STREAM numbers. The Rubin platform blog lists SOCAMM LPDDR5X under resiliency: serviceability and fault isolation sit next to CPU core validation and shorter diagnostics. Operators get a path to swap memory without scrap-the-motherboard drama.

What NVIDIA claims on Vera

Use the official numbers, then keep the footnotes.

Vera itself is an 88-core Olympus design (176 threads) with a unified 164 MB L3 and a second-generation Scalable Coherency Fabric rated at 3.4 TB/s on a monolithic die. The memory story only works if that fabric can keep all cores fed. That is why NVIDIA sells bandwidth per core as hard as raw TB/s.

Host attach for NICs and accelerators still rides PCIe. If you are sizing the non-coherent edge of the box, start with the PCIe 6.0 guide rather than pretending SOCAMM replaces every link in the system.

The June 2026 capacity cut: 192 GB to 96 GB

Marketing "up to" and shipping BOM are different documents. On 9 June 2026, The Elec reported that NVIDIA was cutting SOCAMM2 module capacity from 192 GB to 96 GB because of LPDDR shortages, framed as supply management rather than demand destruction.

The module math in that reporting is concrete. One SOCAMM2 holds four LPDDR5X packages. The original plan stacked four 12 GB dies per package for 192 GB per module. The revised plan uses a two-high stack, landing at 96 GB per module. Each Vera CPU still takes eight modules and 32 package substrates. Substrate count stays; bits per stack fall.

Do the arithmetic before you argue with a rack quote.

• 8 × 192 GB = 1,536 GB ≈ the official "up to 1.5 TB" ceiling.
• 8 × 96 GB = 768 GB per CPU if defaults ship at the cut capacity.
• Because modules are socketed, a later swap to taller stacks or denser dies can raise capacity without a motherboard respin.

SOCAMM vs RDIMM, MRDIMM, HBM, GDDR7, and CXL

The expensive mistake is treating every bandwidth headline as interchangeable DRAM.

If your bottleneck is GPU HBM capacity, buy HBM allocation or model parallelism. If your bottleneck is Xeon host STREAM on DDR5, read the MRDIMM guide. If your bottleneck is Vera-class agentic CPU bandwidth with serviceable LPDDR, SOCAMM is the named part.

MRDIMM: A Full Guide to Multiplexed-Rank DDR5 When RDIMM Runs Out of Bandwidth

The DDR5 DIMM-slot counterpart when host bandwidth outruns ordinary RDIMM.

Inside Deep Tech

Operator playbook: questions that catch fake "up to" quotes

A clean SOCAMM line item in a rack quote still hides several failure modes. Ask these out loud.

• Is the module JESD328 SOCAMM2, or a pre-standard first-gen SOCAMM SKU with a similar name?
• What density ships in the default BOM: 96 GB or 192 GB per module?
• How many sockets are populated at ship, and are empty sockets qualified for later fill?
• What is the measured host bandwidth on the exact CPU SKU, not only the datasheet ceiling?
• What is the RMA path and mean time to replace a failed module in your facility?
• Does the BMC expose SPD and thermal telemetry per module?
• Are LPDDR package vendors dual-sourced on the same raw card?

If the seller answers with a single TB/s number and a smile, you do not have a memory architecture. You have a slogan.

Pair the answers with the rest of the AI interconnect stack. Coherent CPU-GPU traffic is NVLink-C2C on Vera Rubin. Scale-up GPU fabrics and scale-out NICs are a different column, covered in the NVLink, InfiniBand, and UALink guide. SOCAMM does not make those links faster. It stops the host CPU from becoming the quiet bottleneck beside them.

Methodology and sources

This guide uses primary vendor and standards materials dated through early September 2026: NVIDIA's Vera CPU product page, the NVIDIA Vera CPU datasheet PDF, NVIDIA's 6 March 2026-class Rubin platform technical blog ("Inside the NVIDIA Vera Rubin Platform"), JEDEC document listings for JESD328 and JESD328-J0-RCA, and JEDEC's 20 October 2025 SOCAMM2 press preview. Capacity-cut mechanics cite The Elec's 9 June 2026 industry report. Secondary timing notes on the Gen1-to-SOCAMM2 shift are treated as secondary, not as JEDEC text.

Relative performance charts on NVIDIA's site are NVIDIA's measured data and are labeled subject to change. Inside Deep Tech does not invent independent STREAM runs that it did not perform. Where shipping density diverges from "up to" capacity, that gap is called out explicitly.

What JEDEC actually standardized

On 20 October 2025 JEDEC said it was nearing completion of JESD328 for datacenter AI, forecasting support for the full LPDDR5X rate including configurations up to 9.6 Gb/s per pin where platform signal integrity allows, plus SPD for module identity and telemetry. By mid-2026 the common standard and Raw Card A annex were published documents on jedec.org (JESD328 June 2026; JESD328-J0-RCA May 2026).

That sequence matters. A press preview is not a shipping SKU, and a published standard is not automatic multi-vendor availability at 192 GB. Standards remove the "only one company can invent the connector" risk. They do not print LPDDR wafers.

Compression attach, not another DIMM slot

Compression-attached modules sit in a different mechanical family from DDR5 DIMMs. The point of the socket is contact pressure and service loops, not pin-compatibility with an RDIMM key. That is why "can I drop SOCAMM into my Xeon board?" is the wrong question.

What you should ask instead is platform-local: how many sockets, what module density ships by default, what SPD/telemetry the BMC can see, and whether a failed module is a hot-aisle swap or a return-to-depot event. NVIDIA's public language emphasizes field replaceability and fault isolation. Your integrator still has to prove the wrench time.

Form-factor chatter in the secondary market often cites a much smaller outline than a standard RDIMM, which is the whole small-outline pitch: denser board real estate beside a modular CPU package without blocking airflow the way a forest of tall DIMMs can. Treat exact millimeters as a drawing callout from the vendor, not a blog rumor.

LPDDR supply is now an AI-factory constraint

Phones and notebooks used to set LPDDR demand. AI CPUs and AI PCs added another consumer on the same wafer start. The Elec's June 2026 account is useful because it separates demand from density: NVIDIA still wanted the modules and substrates. It shortened the stack so the same LPDDR supply could cover more servers.

That is a familiar deep-tech pattern. HBM had CoWoS and stack constraints. Host LPDDR now has die and package constraints. Operators who only model GPU HBM will miss a second DRAM line item that can gate rack shipments even when the GPUs are allocated.

Inside Deep Tech's practical checklist for buyers:

• Module density on the quote (96 GB vs 192 GB) and whether "up to 1.5 TB" is configured or aspirational.
• Supplier mix for LPDDR5X packages (multi-sourcing reduces single-fab drama).
• Written path to denser modules later without motherboard respin.
• Spare module stock and RMA timing for compression sockets.
• Separate planning lines for HBM, SOCAMM, and DDR5/MRDIMM so one shortage does not get averaged away.

From soldered Grace LPDDR to socketed Vera SOCAMM

The Rubin platform table is the cleanest public before/after. Grace lands around 512 GB/s and 480 GB of LPDDR5X. Vera lands around 1.2 TB/s and 1.5 TB on SOCAMM. Bandwidth roughly 2.4x in that table language, capacity about 3x, while NVLink-C2C doubles to 1.8 TB/s toward Rubin.

Those jumps are why SOCAMM is not a cosmetic socket. Vera's agentic pitch assumes the CPU is busy compiling, sandboxed code, retrieval, and orchestration while GPUs train or serve. Starving that CPU on host DRAM wastes the coherent link you just paid for.

Still keep the boundary. NVLink-C2C moves bytes between Vera and Rubin. SOCAMM feeds Vera's own cores. Mixing those two bandwidth numbers in a slide is how architecture reviews go sideways.

Who should care, and who should wait

Care now if you are buying Vera / Vera Rubin class CPU memory, writing AI-factory RFPs that mention detachable LPDDR, or modeling rack-level DRAM supply against NVIDIA's module counts.

Wait, or at least separate the column, if you are still on soldered Grace boards with no upgrade socket, if your fleet is x86 DDR5 only, or if the real constraint is GPU HBM and CoWoS allocation. SOCAMM will not fix a missing HBM stack.

Named downside: LPDDR demand from phones, PCs, and AI servers now collides. The June 2026 cut shows vendors will ship more racks at lower module density rather than stall the line. Your "up to" slide can silently become a 768 GB CPU until LPDDR6-class modules or taller stacks return.

FAQ

What happens next

Watch three clocks. First, whether default Vera BOMs climb back from 96 GB modules toward the 192 GB ceiling as LPDDR supply eases or LPDDR6-class SOCAMM parts appear. Second, how many non-NVIDIA platforms actually pin JESD328 sockets instead of keeping soldered LPDDR. Third, whether operators keep separate HBM, SOCAMM, and DDR5 lines in capacity planning instead of averaging every "TB/s" into one fantasy number.

The module is real. The standard is published. The shortage is also real. Size the socket, the density, and the upgrade clause, then ship.