CFET: A Full Guide to Stacked Nanosheet Transistors After GAAFET

GAAFET bought leading-edge logic another density chapter by wrapping the gate around stacked nanosheets. It did not invent a second floorplan for CMOS pairs. nFET and pFET still sit side by side.

A complementary FET (CFET) stacks those polarities into one footprint: one device above the other, separated by middle dielectric isolation (MDI). Samsung's Semiconductor Research Center won Best Paper recognition at the 2026 VLSI Symposium for a 3D Stacked FET at 42 nm gate pitch with triple-stacked nanosheet channels in both n and p devices. Imec's May 2026 roadmap call, as reported by IEEE Spectrum, puts commercial CFET introduction around 2033 at the A7 node.

This guide covers how CFET differs from GAAFET nanosheet transistors, why contacted poly pitch (CPP) and track height (5.5T today, 4.5T and 3T with CFET) matter, how monolithic CFET (mCFET) differs from sequential CFET (sCFET), what Intel, Samsung, TSMC, and imec have actually demoed as of September 2026, and where the honest limits sit. Backside power is covered in the PowerVia / backside power guide. Patterning ceilings live in the High-NA EUV guide. Die stacking density is hybrid bonding / SoIC / Foveros Direct. Do not treat CFET as a substitute for packaging, HBM, or CoWoS.

Key Takeaways

• CFET stacks nFET and pFET vertically in one footprint after GAAFET leaves CMOS pairs side by side (IEEE Spectrum / imec roadmap, May 2026).
• Samsung's 2026 VLSI Best Paper showed a 42 nm gate-pitch 3D Stacked FET with triple nanosheets in both polarities and MDI isolation (Samsung Semiconductor tech blog).
• Imec expects commercial CFET around 2033 at A7, with cells moving from ~5.5T GAA toward 4.5T and 3T (IEEE Spectrum; imec Part 1, Sep 2026).
• mCFET is a single process sequence; sCFET patterns top and bottom independently with two wafer flips and harder alignment (imec Part 1).
• Prototypes are not volume chips: process versions remain open, interconnect congestion eats density, and High-NA/EUV still gate patterning.

CFET at a glance

Why CFET comes after GAAFET

Let's start with what GAAFET already fixed. FinFET electrostatics ran out of headroom as fins got thinner. Nanosheet GAA wraps the gate around multiple suspended channels and restores control. Imec's Part 1 article (published about 7 September 2026) states GAA nanosheet scales to about the A10 generation with 5.5-track (5.5T) standard cells.

Here's the problem. Track height is the cell's vertical budget in metal tracks. Shrinking CPP (the contacted poly pitch, the spacing from one transistor gate to the next) helps, but nFET and pFET still consume lateral floorplan when they sit beside each other. At some point the cell can't get shorter without stacking the pair.

That means CFET is the architecture that unlocks 4.5T cells and, on imec's roadmap language, down to 3T, extending classical CMOS scaling toward A3. Imec also frames A7 as the node where CFET becomes the likely device transition, matching Spectrum's May 2026 reporting of commercial introduction around 2033.

On the flip side, CFET doesn't retire EUV. Gate patterning, tip-to-tip, and cut masks still sit on Low-NA or High-NA EUV tools. Stacking transistors is orthogonal to printing finer lines.

How a CFET is built

At first glance, the idea is simple: put PMOS on NMOS (or the reverse) and share a footprint. The process is not.

The likely monolithic path, as Spectrum summarizes from imec, deposits alternating Si/SiGe layers, patterns trenches, then selectively etches SiGe to leave suspended silicon nanosheets. The top set becomes one polarity. The bottom set becomes the other. MDI sits between them so each device can take a different gate stack. Samsung's VLSI write-up stresses that MDI is not cosmetic insulation: n and p need different gate materials, and a too-thin or mis-placed MDI couples the floors of the "apartment."

Imec splits integration into two complementary tracks.

Spectrum notes a bonded/sequential option that grows the top device layers on a second wafer, then bonds them so isolation and crystal orientation can favor PMOS and NMOS separately. Intel has been testing that scheme. Imec still calls mCFET the faster industrial path if alignment for sCFET doesn't catch up.

Who has demoed what

As of September 2026, the big three all have prototype CFETs. That is not the same as a volume process of record.

Samsung brands the device 3D Stacked FET and maps the industry label to CFET. The evolution line in its blog is explicit: Planar → FinFET → GAA → 3D Stacked FET. The 42 nm gate pitch is the density headline versus earlier 48 nm-class public demos discussed in secondary coverage.

First of all, read demos as module readiness, not as a foundry quote. Samsung demonstrated current control and across-wafer uniformity. It did not claim volume production.

GAAFET and Nanosheet Transistors: A Full Guide to How Chips Leave FinFET Behind

The nanosheet chapter CFET extends: why FinFET ran out of room, how GAA wraps the channel, and what shipping nodes actually mean.

Inside Deep Tech

Contacts, MDI, backside power, and multi-Vt

Of course, stacking the channels is only half the bill of materials. You still have to contact the bottom device, isolate the floors, deliver power, and set multiple threshold voltages without eating the nanosheet gap.

Backside contacting of the bottom source/drain improves contact resistance and opens process window for the top device. Imec's 2026 VLSI module pairs a frontside BDI with a backside BDI so the bottom SiGe:B epi isn't seeded by the substrate in a way that wastes contact metal volume. Reported results: bottom pFET drive current 5× versus the conventional backside scheme, access resistance from 1753 to 378 Ω·µm, and survival yield from 45% to 85%.

That module sits next to the broader industry move of putting power rails under the transistor layer. If you're sizing racks and dies, read the backside power delivery guide in parallel. CFET makes backside contacts more valuable. It does not invent PowerVia.

For multi-Vt, space between nanosheets is too tight for thick work-function metal stacks. Imec's dipole-middle gate stack locks a La-based shifter in a thin HfO2 sandwich at lower thermal budget, aiming compatibility with low-temperature CFET replacement metal gate flows. The 2026 VLSI demo showed about a 30 mV nFET Vt reduction versus a reference where the shifter was removed before lock-in.

Here's why that matters for buyers: a CFET node that can't offer multiple Vt flavors is a science project. Logic libraries need HVt/LVt/SVt corners even when the devices are stacked.

Honest limits

Prototypes are not production. Imec's commercial intro call is around 2033. That is seven years of module engineering after the 2026 demos, not a 2027 SKU.

• Process version still open. Paul Heremans told Spectrum that many CFET versions remain open. mCFET vs sCFET, isolation schemes, and contact flows are competing pathfinding tracks, not a frozen POR.
• Interconnect congestion eats density. Shorter cells pack more gates, then the BEOL has to route them. Imec's Part 2 agenda explicitly studies BEOL routability for CFET standard cells. Area wins on the device can shrink at the block level.
• Not a packaging substitute. CFET densifies CMOS pairs on a logic die. It does not replace HBM stacks, CoWoS interposers, or hybrid-bonded chiplets. Those remain separate bottlenecks.
• Lithography still gates patterning. CPP and tip-to-tip still need EUV, including High-NA where foundries choose it. Stacking doesn't print a smaller pitch by itself.
• Yield and thermal history. Tall stacks, wafer flips, and low-temperature RMG constraints make survival yield a first-class metric. Imec publishing 45%→85% on bottom pFET survival is the tell: yield is still the story.

Inside Deep Tech's take

What happens next

Through late 2026 and 2027, watch three signals. First, whether mCFET stays the industrial favorite or sCFET alignment numbers close the gap. Second, whether backside contact and MDI modules keep posting yield and resistance wins at tighter CPP. Third, whether DTCO papers show 3T cells that remain routable without exploding metal pitch.

Further out, Spectrum's May 2026 imec roadmap piece puts a later CFET evolution phase, then roughly 2041 interest in swapping silicon channels for 2D semiconductors such as MoS2, mainly for power. In parallel, imec's CMOS 2.0 story stacks heterogeneous functional tiers with dense 3D interconnects. Wafer-to-wafer bonding pitches in development around 200 nm imply on the order of 25 million interconnects per mm². That packaging density is why hybrid bonding stays on the same reading list as CFET.

Operators and investors should keep CFET on the transistor roadmap column, GAAFET on the shipping column, and packaging on its own column. Mixing those columns is how decks invent phantom density.

FAQ

Primary sources for this guide include Samuel K. Moore's May 19, 2026 IEEE Spectrum report on imec's semiconductor technology roadmap (spectrum.ieee.org/semiconductor-technology-roadmap), Samsung Semiconductor's 2026 VLSI Best Paper tech blog on 3D Stacked FET at 42 nm gate pitch (semiconductor.samsung.com tech blog), and imec's September 2026 Part 1 article on CFET integration modules and standard-cell scaling (imec-int.com CFET Part 1). Historical demo pitches cite Spectrum's December 16, 2023 CFET overview. Figures are dated as of September 2026 editorial review.