GDDR7: A Full Guide to Board-Level Bandwidth When HBM Is Overkill

Not every AI accelerator needs a silicon interposer and a stack of HBM. Some workloads want high bandwidth soldered to the PCB, at a power and packaging cost that does not look like a CoWoS allocation fight. That is the job GDDR7 took in 2026 — and mistaking it for "HBM for gamers" is how a BOM overpays for packaging it never needed, or underbuys the memory class a training rack still requires.

JEDEC published JESD239 GDDR7 on 5 March 2024 as the first JEDEC DRAM standard to use PAM signaling. Micron ships introductory parts at up to 32 Gb/s with more than 1.5 TB/s system bandwidth on a 384-bit bus. NVIDIA's GeForce RTX 5090 puts 32 GB of GDDR7 on a 512-bit interface at 1.792 TB/s. On 9 September 2025, NVIDIA announced Rubin CPX with 128 GB of cost-efficient GDDR7 for massive-context inference, expected available by the end of 2026. The useful question is which memory tier you are buying for, not whether "GDDR replaced HBM."

This is the board-level graphics-memory guide. Stacked near-memory for training and data-center GPUs lives in the HBM guide. The packaging lines that make HBM attach possible are TSMC CoWoS and hybrid bonding. Host and peripheral attach for discrete cards is still PCIe 6.0. Host memory expanders are CXL. We do not re-derive them here.

Key takeaways

• JEDEC JESD239 GDDR7 (5 March 2024) doubles per-device bandwidth versus GDDR6, up to 192 GB/s per device. It is the first JEDEC DRAM standard to use PAM signaling.
• PAM3 is the core trick. Three voltage levels transmit 3 bits over 2 cycles, versus NRZ's 2 bits over 2 cycles. That raises data rate per cycle without jumping straight to PAM4's tighter voltage margins.
• Channels double: four independent channels versus two on GDDR6. Densities in the standard framing run from 16 Gbit to 32 Gbit, with RAS features including on-die ECC.
• Micron's introductory GDDR7 hits 32 Gb/s and 128 GB/s per component. On a 384-bit bus that is greater than 1.5 TB/s system bandwidth, at 1.2 V versus GDDR6's 1.35 V, with Micron quoting 4.5 pJ/bit versus 6.5 pJ/bit on GDDR6.
• Samsung positions GDDR7 for AI as well as graphics. Its first 16Gb GDDR7 targeted 32 Gbps and 1.5 TB/s card-level bandwidth; a later 24Gb GDDR7 announcement cites speeds over 40 Gbps for next-generation AI computing validation.
• RTX 50-class GeForce cards ship GDDR7 today. NVIDIA's RTX 5090 page lists 32 GB GDDR7 on a 512-bit interface; NVIDIA's Blackwell architecture whitepaper puts peak bandwidth at 1.792 TB/s at 28 Gbps GDDR7.
• Rubin CPX is the data-center proof that GDDR7 is not only a gaming story. NVIDIA's 9 September 2025 announcement puts 128 GB of GDDR7 on a context-phase inference GPU expected at end of 2026.
• Buying GDDR7 as a drop-in for HBM on a training GPU is the expensive mistake. Different attach, different capacity density per package, different power-per-bit and BOM. GDDR7 wins when the interposer is overkill. HBM wins when the workload is memory-wall training at multi-TB/s per GPU.

GDDR7 at a glance

What JEDEC actually standardized

Start with the date and the document. On 5 March 2024, JEDEC announced publication of JESD239 Graphics Double Data Rate (GDDR7) SGRAM. The press release is blunt on the headline: double the bandwidth over GDDR6, reaching up to 192 GB/s per device, aimed at graphics, gaming, compute, networking, and AI.

The signaling change is the story. JESD239 is the first JEDEC standard DRAM to use a Pulse Amplitude Modulation interface for high-frequency operation. PAM3 uses three levels (+1, 0, −1) to transmit 3 bits over 2 cycles, versus traditional NRZ transmitting 2 bits over 2 cycles. JEDEC frames that as higher data transmission rate per cycle with better SNR for high-frequency operation and improved energy efficiency relative to pushing NRZ harder.

Architecture details JEDEC called out in the same release:

• Four independent channels, doubling GDDR6's two.
• Densities from 16 Gbit to 32 Gbit, including 2-channel mode language for capacity configurations.
• RAS focus: on-die ECC (ODECC) with real-time reporting, data poison, error check and scrub, command/address parity with blocking (CAPARBLK), and LFSR training patterns with eye masking and error counters.

That RAS list matters for AI inference cards and cloud gaming nodes that cannot treat graphics memory as a best-effort framebuffer. GDDR7 is still discrete DRAM on a board. It is not "HBM without the stack." It is the graphics-memory line grown up enough that JEDEC put data-center RAS language in the announcement.

PAM3 versus NRZ and why not PAM4

GDDR6 used NRZ. GDDR6X (NVIDIA's Micron partnership path) used PAM4 on the graphics bus. GDDR7 standardized on PAM3.

The tradeoff is signal integrity versus bits per cycle. PAM4 packs 2 bits per unit interval with four voltage levels — powerful, but the eyes get small. PAM3 sits in the middle: 1.5 bits per cycle on average (3 bits / 2 cycles), with three levels instead of four. JEDEC's public framing emphasizes SNR and energy efficiency at high frequency. Micron's GDDR7 materials add a vendor claim that PAM3 improves margin versus GDDR6/6X and supports scaling toward 40 Gb/s and beyond in characterization — treat the 40 Gb/s eye as Micron lab characterization, not a JEDEC mandatory rate.

For board designers, the practical consequence is familiar from other multilevel buses: return loss, crosstalk, equalization, and training get harder as pin rate climbs past the mid-20s Gb/s. GDDR7 does not invent new PCB physics. It asks more of the same BGA breakout and layer stack.

Bandwidth math that operators actually quote

Per-device and per-card numbers get mixed in slide decks. Keep the columns separate.

Rough mental model for a 32-bit GDDR7 device: bandwidth (GB/s) ≈ (Gb/s per pin × 32) / 8. At 32 Gb/s that is 128 GB/s per chip. At 48 Gb/s that is 192 GB/s per chip — the JEDEC ceiling number. A 384-bit GPU bus with twelve 32-bit devices at 32 Gb/s lands near 1.5 TB/s. A 512-bit bus at 28 Gb/s lands at NVIDIA's 1.792 TB/s for the 5090. Always check whether the slide is quoting pin rate, per-device bandwidth, or full GPU aggregate.

GDDR7 versus HBM: different jobs

Four rows. One expensive spreadsheet if you merge them.

HBM's advantage is package-level bandwidth density and energy when the workload saturates multi-TB/s and large on-package capacity. GDDR7's advantage is board-level bandwidth without the interposer. NVIDIA's own Rubin CPX language calls GDDR7 "cost-efficient" memory for a context-phase GPU — that is the vendor admitting the packaging tier is a product decision, not a status contest.

For the packaging bottleneck behind HBM attach, read CoWoS and hybrid bonding. GDDR7 mostly skips that queue. It joins a different queue: high-speed PCB design and DRAM wafer allocation.

Where GDDR7 shows up in 2026 products

Consumer and prosumer GPUs. NVIDIA's GeForce RTX 5090 product page lists 32 GB of GDDR7 on a 512-bit memory interface. The Blackwell architecture whitepaper states the 5090 ships 28 Gbps GDDR7 for 1.792 TB/s peak bandwidth, and the 5080 ships 30 Gbps GDDR7 for 960 GB/s. NVIDIA's CES-era GeForce news framed Blackwell as launching with GDDR7 and cited up to roughly 1.8 TB/s class bandwidth on the high end. That is shipping product language, not a roadmap slide.

Vendor DRAM. Micron's GDDR7 product page and product brief position 1β-process parts at up to 32 Gb/s, 128 GB/s per component, and >1.5 TB/s on a 384-bit system bus, with lower voltage and better pJ/bit than their GDDR6 reference table. Samsung's July 2023 development announcement claimed industry-first GDDR7 at 32 Gbps and 1.5 TB/s card bandwidth with PAM3; its later 24Gb GDDR7 release pushes pin rate past 40 Gbps for AI computing validation. Attribute densities and dates to the specific press release — vendors ship multiple SKUs.

Data-center inference, selectively. On 9 September 2025, NVIDIA announced Rubin CPX: up to 30 petaFLOPS NVFP4, 128 GB of GDDR7, hardware video encode/decode, and 3× attention acceleration versus GB300 NVL72 on NVIDIA's stated comparison. Rubin CPX pairs with Vera CPUs and Rubin GPUs inside Vera Rubin NVL144 CPX. NVIDIA said availability is expected at the end of 2026. That single product is the cleanest primary-source proof that GDDR7 has a deliberate AI-infra role beyond GeForce: context-phase throughput where cost-efficient board memory beats another HBM stack.

What still stays on HBM. Flagship training GPUs and many data-center inference SKUs remain HBM-class. Do not read Rubin CPX as "HBM is dead." Read it as disaggregated inference letting different memory economics on different phases.

PCB reality: the cost you do not see on the JEDEC slide

HBM moves the hard routing onto the package. GDDR7 leaves it on the motherboard.

At 28–32+ Gb/s PAM3 across many devices, breakout, length matching, via stubs, and power integrity dominate layout reviews. Micron's package notes (12 × 14 mm class, 266-ball counts in the product brief) are not hobbyist footprints. Clamshell configurations and dual-rank-ish topology tricks from earlier GDDR generations still interact with signal integrity budgets.

Honest constraints:

• Layer count and materials. Cheap FR-4 stackups that survived mid-GDDR6 may not survive a 512-bit 28 Gbps design without tears.
• Power delivery. More simultaneous switching at high pin rates stresses PDN design even when the DRAM voltage dropped to 1.2 V class.
• Thermal. Board-level DRAM still dumps heat into the card; vapor chambers sized for the GPU die are not automatically sized for a ring of hot GDDR7 packages.
• Supply. Graphics DRAM wafer starts compete with HBM and DDR allocation. A "GDDR7 is cheaper than HBM" sentence can be true on packaging and false on spot market pricing in a tight year.

This guide will not invent insertion-loss budgets that are not on a cited vendor channel guide. If a module vendor quotes a reach number, ask for the stackup and the eye mask that produced it.

A realistic timeline

The bottom line

2026 is the year GDDR7 stopped being only a GeForce checkbox. JEDEC standardized PAM3 graphics memory at up to 192 GB/s per device. Micron and Samsung are shipping and validating parts in the 32–40+ Gb/s class. NVIDIA put GDDR7 on RTX 50 cards at up to 1.792 TB/s on the 5090 and announced 128 GB of GDDR7 on Rubin CPX for long-context inference.

Inside Deep Tech's take: treat GDDR7 as the board-level bandwidth tier for workloads that do not justify an interposer — gaming, edge, cost-sensitive inference, and context-phase accelerators. Keep HBM for the memory-wall GPUs where packaging cost buys multi-TB/s and on-package capacity. The named downside is blunt: PAM3 at these pin rates is a PCB and supply problem, and using GDDR7 to "save money" on a training GPU that still needs HBM bandwidth density is how you buy a card that looks fine on a spreadsheet and fails on the memory wall.

Ask three questions of any GDDR7-versus-HBM pitch. What is the attach — board BGA or interposer stack? What is the measured system bandwidth and capacity on the real bus width, not the per-pin brochure? Which phase of the workload is this memory for — training, decode, context prefill, or graphics? Vendors that answer cleanly are doing memory-system engineering. Vendors that only say "faster than GDDR6" are selling a generation number.

Frequently asked questions

What is GDDR7?

Graphics Double Data Rate 7, JEDEC standard JESD239 (published 5 March 2024). It is board-level high-bandwidth DRAM using PAM3 signaling, aimed at graphics, gaming, compute, networking, and AI.

How fast is GDDR7?

JEDEC cites up to 192 GB/s per device. Micron's introductory parts run up to 32 Gb/s (128 GB/s per component; >1.5 TB/s on a 384-bit bus). NVIDIA's RTX 5090 reaches 1.792 TB/s with 28 Gbps GDDR7 on a 512-bit interface per the Blackwell architecture whitepaper.

What is PAM3?

Pulse Amplitude Modulation with three levels. JEDEC: PAM3 sends 3 bits over 2 cycles versus NRZ's 2 bits over 2 cycles, raising data rate per cycle for high-frequency DRAM I/O.

How is GDDR7 different from HBM?

GDDR7 packages solder to the PCB. HBM stacks sit on an advanced package/interposer beside the GPU. Different bandwidth density, power, capacity, and cost structures. See the HBM guide.

Does GDDR7 replace HBM in AI data centers?

No as a blanket rule. Flagship training GPUs still depend on HBM. NVIDIA's Rubin CPX shows GDDR7 can be the deliberate choice for a context-phase inference GPU (128 GB GDDR7, expected end of 2026). Tier the memory to the phase.

Which products use GDDR7 today?

GeForce RTX 50-series cards (for example RTX 5090: 32 GB GDDR7). Micron and Samsung GDDR7 DRAM products. Rubin CPX announced with GDDR7 for end-2026 availability.

How many channels does GDDR7 have?

Four independent channels in the JEDEC announcement framing, double GDDR6's two.

Is GDDR7 the same as GDDR6X?

No. GDDR6X was a prior Micron/NVIDIA PAM4 graphics-memory path. GDDR7 is the JEDEC PAM3 standard generation with its own channel count, RAS feature set, and vendor roadmaps.

Will higher GDDR7 speeds fix the AI memory wall alone?

No. Pin rate helps discrete cards and selected inference SKUs. Training-scale memory walls still push HBM capacity, packaging throughput (CoWoS), and sometimes host-side expanders (CXL).

Methodology

Primary sources as of 4 September 2026: JEDEC JESD239 GDDR7 publication announcement (5 March 2024; up to 192 GB/s per device; first JEDEC DRAM with PAM; PAM3 3 bits/2 cycles vs NRZ 2 bits/2 cycles; four channels; 16–32 Gbit densities; RAS/ODECC feature list). Micron GDDR7 product page and Micron GDDR7 product brief (32 Gb/s intro; 128 GB/s per component; >1.5 TB/s on 384-bit; 1.2 V; 4.5 vs 6.5 pJ/bit; four channels). Samsung GDDR7 development announcement (32 Gbps; 1.5 TB/s; PAM3) and Samsung 24Gb GDDR7 announcement (>40 Gbps / up to 42.5 Gbps). NVIDIA GeForce RTX 5090 (32 GB GDDR7, 512-bit). NVIDIA RTX Blackwell GPU Architecture PDF (5090: 28 Gbps → 1.792 TB/s; 5080: 30 Gbps → 960 GB/s; PAM3 notes). NVIDIA Rubin CPX newsroom release (9 September 2025; 128 GB GDDR7; 30 PFLOPS NVFP4; end-2026 availability). HBM and packaging comparisons deferred to cited Inside Deep Tech guides rather than re-derived here. No invented bandwidth tables.