MRDIMM: A Full Guide to Multiplexed-Rank DDR5 When RDIMM Runs Out of Bandwidth

Core counts on Intel Xeon 6 keep climbing. Memory bandwidth per core has not kept pace on ordinary DDR5 RDIMMs. That gap shows up in HPCG, STREAM, small-model inference, CFD, and any job that stalls waiting on host DRAM instead of waiting on the GPU fabric.

The industry answer sitting in the same DIMM slot is MRDIMM, Multiplexed Rank DIMM: on-module buffers that let two ranks feed the CPU in the same unit of time. Shipping Gen1 class parts run near 8800 MT/s on Intel Xeon 6 platforms that still talk 6400 MT/s RDIMM as the common baseline. JEDEC's 30 April 2026 update put Gen2 raw cards on a 12,800 MT/s target while publishing the next MDB standard.

This guide covers what MRDIMM is, how it differs from MCRDIMM naming, what Micron and Intel claim, what Phoronix actually measured, where the JEDEC roadmap goes, and what it is not. Near-package GPU memory lives in the HBM guide. Host expanders are CXL. Board-level graphics DRAM is GDDR7. Do not merge those columns on a BOM.

Key Takeaways

• MRDIMM (Multiplexed Rank DIMM) uses on-DIMM MRCD and MDB buffers so two ranks operate in parallel, delivering about 128 bytes per cycle versus 64 on a conventional DDR5 DIMM (Intel support article 000098737).
• Shipping Gen1 class runs near 8800 MT/s on Intel Xeon 6, versus a common RDIMM compare baseline of 6400 MT/s; Intel Newsroom (15 Nov 2024) frames that as roughly a 40% peak bandwidth step and cites independent tests with jobs up to ~33% faster.
• Micron lists modules from 32 GB to 256 GB, claims about a 39% bandwidth upgrade versus RDIMM 6400 (Intel MLC, 128 GB vs 128 GB), and up to ~40% lower latency on Llama 3 8B empirics (same capacity footnote). Gen1 is Xeon 6 only.
• JEDEC on 30 April 2026 published JESD82-552 (DDR5MDB02); MRCD02 (JESD82-542) expected soon; Gen2 module standard nearing completion; Gen2 raw cards targeting 12,800 MT/s; Gen3 in development.
• Honest limits: MRDIMM is not HBM, not CXL pooling, and not a free lunch on power. Phoronix's Sep 2025 revisit saw roughly 8% geo-mean across ~75 benches, with HPCG near 24%, and higher DIMM power and temperature.

MRDIMM at a glance

Naming: MRDIMM, MCRDIMM, MRCD, MDB

Start with the labels. You will see four acronyms in datasheets and support pages.

MRDIMM is the JEDEC name: Multiplexed Rank Dual Inline Memory Module. That is the term to use in RFPs and standards talk.

MCRDIMM (also written MCR DIMM) is the earlier product naming path associated with SK hynix and Intel: Multiplexed Combined Rank / Multiplexer Combined Ranks. Intel's support article 000098737 still titles the topic as Multiplexed Combined Rank DIMM and treats MCR DIMM or MRDIMM as the same high-performance DDR5 class for Xeon 6. Treat MCR as Gen1-era marketing synonymy, not a second incompatible form factor.

MRCD is the Multiplexed Rank Registering Clock Driver. It is the registering clock path upgraded for multiplexed-rank command and address handling.

MDB is the Multiplexed Rank Data Buffer. JEDEC published JESD82-552 (DDR5MDB02) on 30 April 2026 as the next-generation MDB definition. The companion JESD82-542 (DDR5MRCD02) was listed as expected soon in the same JEDEC announcement.

If a vendor slide says "MCR" and a JEDEC slide says "MRDIMM," ask which generation of MRCD/MDB silicon and which CPU enablement list, not whether the gold fingers look different. The connector is still an RDIMM-compatible slot on supported platforms.

The core trick: two ranks in the same unit of time

Most server DIMMs already have two ranks. On a conventional RDIMM, those ranks are independent for capacity, but the host still accesses them one at a time. You get capacity. You do not get simultaneous rank bandwidth.

Intel's 15 November 2024 Newsroom piece quotes George Vergis on the design insight: parallel resources were sitting unused. Put a mux buffer on the module, let data flow across both ranks in the same unit of time, and consolidate the electrical load so the interface can run faster than a comparable RDIMM.

Intel's support language makes the byte math explicit: MCR/MRDIMM enables 128 bytes of data transfer per cycle instead of the standard 64 bytes, and targets rates around 8800 MT/s. Lenovo Press LP2028 frames the same idea for operators: two ranks feeding the CPU at once doubles the bytes delivered relative to a regular DDR5 DIMM access pattern.

SemiEngineering and Rambus-style explainers call the buffer path a gearbox: DRAM ranks can stay at a native data rate while the host-facing channel runs at a higher effective rate. That is why Gen2 roadmaps talk about 12,800 MT/s host-side rates built on parallel rank access rather than asking every DRAM die to magically double its own pin rate in isolation.

On a dual-rank RDIMM without muxing, rank A and rank B take turns on the channel. Interleaving still helps hide latency and raise effective throughput across banks, but it is not the same as presenting two ranks' worth of data width to the host in one cycle. MRDIMM's claim is the second pattern: parallel rank data, multiplexed onto the existing pin count.

That also explains the buffer cost. You are adding MRCD and multiple MDB devices, a higher-power PMIC class on the module roadmap, and more switching energy. Intel and Micron sell the bandwidth. Phoronix measures the watts. Both belong in the same purchase memo.

Bandwidth math operators actually quote

Keep pin rate, per-module bandwidth uplift, and application speedup in separate columns.

Here's why that matters. A STREAM or MLC slide can look like a 30-40% story. A mixed Linux suite can land near single-digit geo-mean with selective 20%+ wins. Both can be true. Budget for the workload class you run, not the slide deck you liked.

What Micron and Intel are shipping

Micron Gen1 product claims

The product page positions DDR5 MRDIMM as high-bandwidth, low-latency main memory for AI and HPC on Intel Xeon 6, with capacities from 32 GB to 256 GB and transfer rates up to 8.8K MT/s. The FAQ is blunt: Gen1 supports Xeon 6 only; it is not compatible with older Intel Xeon processors. Gen2 design is under definition at JEDEC; Micron says products will support that standard when released.

The 39% bandwidth and ~40% latency claims are footnote-bound empirics against 128 GB RDIMM 6400, not magic multipliers for every SKU and every job. Micron also markets STAC-A2 financial risk-analysis results with Intel processors as a vendor performance mark. Treat STAC as a named vendor claim, not a universal TCO proof.

Intel Xeon 6 platform story

Xeon 6 with Performance-cores (Granite Rapids) is the first CPU family to benefit in production language. Newsroom framing: same connector and form factor as RDIMM, mux chips in previously empty spots, same RAS features, and the option to order MRDIMM at purchase or swap later without code changes. Workloads called out include weather modeling, CFD, small language models, traditional deep learning, and recommendation-style AI that still run well on Xeon.

OEM adoption language in the same piece cites HPC labs and partners such as NEC. Lenovo Press documents ThinkSystem V4 servers with Xeon 6 P-cores as MRDIMM-capable examples (SR650 V4, SR630 V4, SC750 V4 among them).

For the rest of the host stack, keep PCIe 6.0 as the peripheral/host link story and NVLink / InfiniBand / UALink as the GPU fabric story. MRDIMM feeds the CPU socket. It does not replace the GPU interconnect.

Related reading on the near-package memory tier MRDIMM does not replace:

High Bandwidth Memory (HBM): A Full Guide

Package-attached stacked DRAM for AI GPUs and accelerators. Different job than host DDR5 MRDIMM.

Inside Deep Tech

Independent numbers: Phoronix nuance

Vendor peaks are not a substitute for a long Linux suite. Phoronix's original Granite Rapids MRDIMM coverage and the September 2025 revisit on a Giga Computing R284-A92-AAL1 with a single Xeon 6980P are the clearest public apples-to-apples sets.

Configuration: 12× DDR5-6400 64 GB Micron RDIMMs versus 12× MRDIMM-8800 Micron modules, Ubuntu Server 25.10 daily / Linux 6.17 / GCC 15.2 on the revisit. Synthetic memory benches show the raw bandwidth advantage you expect. Across roughly 75 mixed benchmarks, MRDIMM landed about 8% faster on geometric mean. Memory-sensitive HPC and AI jobs sat well above that: HPCG around 24%, and a number of generative AI workloads at least 10%.

Power and thermals are the part slide decks skip. On that air-cooled 2U, BMC-reported average server power moved from about 619 W with DDR5-6400 to about 712 W with MRDIMMs, roughly 7-8 W per module. Peak power in the most demanding memory-intensive apps moved from about 1014 W to 1288 W. Sampled DIMM temperature ran about 5°C warmer on the MRDIMM set.

That is the honest operator math: buy MRDIMM when the job is bandwidth-bound and the uplift pays for ASP plus watts. Do not buy it because the DIMM slot still fits.

JEDEC Gen2 and Gen3 roadmap (dated)

On 30 April 2026, JEDEC announced milestones from JC-40 and JC-45:

• Published: JESD82-552 (DDR5MDB02) Multiplexed Rank Data Buffer
• Expected soon: JESD82-542 (DDR5MRCD02) Multiplexed Rank Registering Clock Driver
• In progress: MRDIMM Gen2 module standard nearing completion
• In development: Gen2 DDR5 MRDIMM raw card designs targeting 12,800 MT/s, plus MRDIMM Gen3 module standard work

That is the standards timeline to put in an architecture review. Gen2 pin-rate targeting 12,800 MT/s is a raw-card / module roadmap number. It is not proof that every Xeon or EPYC SKU ships that rate on a given quarter.

Vendor Gen3 chipset (label clearly). Renesas announced Gen3 MRDIMM chipset solutions (MRCD RRG5013, MDB RRG5103) claiming up to 16,000 MT/s, sampling to select customers including major DRAM suppliers, with production expected in 2H/2027. That is Renesas chipset marketing, not a JEDEC shipping module on a shelf today. Secondary coverage sometimes frames JEDEC Gen3 toward a 17,600 MT/s class over a longer horizon. Keep vendor chipset MT/s and JEDEC module-generation language in separate rows.

Distinguish three calendars when you plan a rack:

1. JEDEC document calendar (MDB02 published 30 Apr 2026; MRCD02 expected soon; Gen2 module standard nearing completion).
2. Raw-card / pin-rate calendar (Gen2 designs targeting 12,800 MT/s).
3. CPU and OEM enablement calendar (which Xeon or future AMD steppings list which MRDIMM speed bins as validated).

Mixing those three is how a roadmap slide becomes an unfulfilled PO. Gen1 at ~8800 MT/s on Xeon 6 is the shipping fact as of September 2026. Gen2 at 12,800 is the standards target to track. Renesas Gen3 chipset sampling toward 16,000 MT/s with 2H/2027 production is supply-chain foreshadowing for buffer silicon, not a reason to mark Gen1 as obsolete this quarter.

What MRDIMM is not

How to size a purchase without lying to yourself

Start with channel count and capacity per core, not with MT/s envy. A partially populated MRDIMM config can beat a fully populated RDIMM config on bandwidth-bound codes, or lose on TCO if the job is not memory-bound. Market reporting through 2025-2026 has also shown MRDIMM ASP volatility as supply and demand catch up; treat sticker prices as quotes, not as a fixed tax in a three-year model.

A practical Monday checklist for operators:

1. Confirm the exact Xeon 6 SKU and BIOS/MRC revision on the OEM MRDIMM support list.
2. Match capacity: compare 128 GB RDIMM 6400 to 128 GB MRDIMM 8800 before you invent a capacity change.
3. Populate the same channel count in both arms of the A/B test.
4. Run Intel MLC or equivalent, STREAM, one HPC or serving binary you actually ship, and capture BMC power.
5. Only then scale the BOM. Fleet-wide MRDIMM without a measured win is how memory spend outruns CPU spend.

If the workload is GPU-bound on HBM, stop. MRDIMM will not move that needle. If the workload is capacity-starved beyond socket DRAM, read CXL before you stack taller DIMMs and hope.

Inside Deep Tech's take

What to do Monday

If you run Xeon 6 P-core servers on memory-bound CPU jobs, ask the OEM for an RDIMM 6400 versus MRDIMM 8800 quote on the same capacity and channel count, then run your own STREAM, MLC, and one production trace. If your pain is GPU HBM or fabric, stay in the HBM and interconnect guides. If your pain is capacity beyond the socket, read CXL. Gen2 JEDEC closure and platform enablement calendars are the dates to put on the architecture board for 2027 planning, not a reason to delay measuring Gen1 where it already ships.

FAQ

Host memory is only one layer of the AI rack. For pooling and expansion beyond the socket, continue here: