Co-Packaged Optics: A Full Guide to CPO, LPO, and Why AI Switches Are Absorbing the Transceiver

A co-packaged optical engine is not a new kind of laser. It is a packaging decision: take the photonics that used to live in a pluggable QSFP or OSFP module at the front panel and sit it a few millimeters from the switch ASIC — and, later, from the GPU. The part operators used to swap when a transceiver died becomes a die on the same substrate as the SerDes.

That decision exists because the alternative is eating the power budget. When Broadcom delivered Bailly in March 2024 — eight 6.4 Tbps silicon-photonic engines around a 51.2 Tbps Tomahawk 5 — it said DSP-based pluggables already consumed about half the watts and half the bill of materials of a traditional switch system. 800G ports made the electrical hop from ASIC to cage expensive. 1.6T makes it worse. CPO's pitch is to delete that hop.

What changed in 2026 is not that co-packaged optics was invented. It is that the first production CPO switches are no longer booth demos, TSMC's Compact Universal Photonic Engine is entering CoWoS-based production, and linear pluggable optics (LPO) is the competing, still-swappable answer to the same power problem. The useful question is which of those architectures is a shipping SKU, which is a foundry roadmap, and why the GPU package is still mostly copper.

Key takeaways

• CPO puts the optical engine on the ASIC package. It does not put a laser inside the GPU. The 2026 products that exist — Broadcom Tomahawk 5 Bailly, NVIDIA Quantum-X Photonics — are Ethernet and InfiniBand switches. Scale-up inside a rack is still copper and HBM. Scale-out across racks is where the optics moved.
• The power win is the missing DSP and the missing centimeters of board. Broadcom's published Bailly KPI is 5 W of optical-interconnect power per 800 Gbps, including laser power, against roughly 14 W/800G for a DSP pluggable — a 60–70% cut. NVIDIA's hardware docs put package-level insertion loss at about 4 dB versus about 22 dB through a traditional pluggable path.
• LPO is not CPO. Linear pluggable optics keep the QSFP/OSFP cage and delete (or starve) the module DSP, pushing equalization onto the host SerDes. You still swap a module. You do not get CPO's millimeter electrical reach or its faceplate density. Treat LPO as the field-replaceable compromise, not as a synonym.
• External lasers are the serviceability patch. Both Broadcom (remote laser modules) and NVIDIA (removable external light sources, 18 modules on the Q3450-LD) keep the temperature-sensitive, field-replaceable part off the ASIC package. The optical engine is co-packaged. The laser, in production designs, usually is not.
• TSMC COUPE is the foundry layer, not a switch SKU. TSMC's 2024 symposium described COUPE as SoIC-X stacking of an electrical die on a photonic die, qualified first for small-form-factor pluggables in 2025 and for CoWoS-based CPO in 2026. The 2026 symposium put COUPE-on-substrate into production this year, claiming 2× power efficiency and 10× lower latency versus a board-level pluggable, with a 200 Gbps micro-ring modulator as the featured device.
• GPU-package optical I/O is a roadmap, not a 2026 bill of materials. Putting a photonic engine next to an XPU on the same interposer is the logical next chiplet. UCIe raw mode was written with that socket in mind. Shipping AI accelerators in 2026 still leave the package over copper and HBM, and send light out through a switch.

CPO at a glance

What co-packaged optics actually is

Start with the thing it is not. It is not photonic computing — no matrix multiply happens in the waveguide. It is not a synonym for silicon photonics, which is the materials and device platform (modulators, detectors, waveguides on a silicon wafer) that CPO, LPO, and modern pluggables all draw from. And "optics next to the GPU" on a keynote slide does not tell you whether the engine sits on the GPU's CoWoS interposer, on a switch in the same rack, or in an OSFP on the faceplate.

A conventional 800G DR8 or FR4 pluggable is a self-contained product: DSP, drivers, TIAs, photonic chip, laser, and a gold-finger connector. The switch ASIC drives a long-reach SerDes across the board, through a connector, into that module. Every generation of lane speed — 50G, 100G, 200G — makes that board channel harder. The DSP spends watts recovering a signal that was clean a few millimeters from the ASIC and ugly 15 cm later.

CPO inverts the stack. The photonic engine sits on the package. The electrical interface is an extra-short-reach (XSR) or on-package link, not a cage-facing SerDes. Fiber, not a pluggable, comes to the faceplate. The OIF's first co-packaging standard, the 3.2 Tb/s Co-Packaged Module Implementation Agreement (OIF-Co-Packaging-3.2T-Module-01.0), is the interoperable version of that idea: a 3.2T engine with 32× CEI-112G-XSR electrical lanes and 8×400G FR4 or DR4 optical ports, sixteen of them around a 51.2T switch, at about 140 G/mm of shoreline. Real silicon has not waited for every vendor to implement that exact module. Broadcom's Bailly engines are 6.4T, not 3.2T. NVIDIA's Quantum-X engines are built around 200G SerDes. The OIF document is the common language, not the SKU list.

Three neighboring architectures get flattened into "CPO" in vendor copy. They are not the same product.

Pluggable, LPO, NPO, CPO

DSP pluggable (QSFP-DD, OSFP). The incumbent. Full DSP in the module, field-replaceable, multi-vendor, and the reason a 51.2T box can still be serviced with a bag of transceivers. Power is the tax: Broadcom's public comparison put a DSP 800G path at about 14 W. At 1.6T the module DSP does not get cheaper.

Linear pluggable optics (LPO). Same cage, no (or almost no) module DSP. The host SerDes equalizes a linear optical path. You keep swapability and a lot of the ecosystem. You give up some reach, some multi-vendor forgiveness, and you still drive centimeters of board. LPO is the 2025–2027 answer for operators who will not put a non-replaceable engine on a switch ASIC. It is not on-package optics.

Near-packaged optics (NPO). Engines on the same board, a few centimeters away, often on a socketed or connectorized substrate. A halfway house that showed up in early CPO debates when nobody wanted to yield optics on the ASIC package. It is a board-design choice, not a 2026 volume category of its own.

Co-packaged optics (CPO). Engines on the ASIC package. Electrical reach in millimeters. Faceplate is fiber (LC, MPO) or a proprietary connector. Lasers are usually remote. Service model changes: you replace a laser module or, in the limit, the switch.

The honest split: LPO competes with CPO for the next pluggable generation's power budget. CPO competes with copper for whether a 102.4T or 409.6T switch can exist at all without melting the faceplate.

Why the cage ran out of watts

The physics is not exotic. A 112G or 224G SerDes driving a lossy board trace needs equalization, and equalization is heat. Move the conversion to light closer to the ASIC and two things improve at once: the electrical channel shrinks, so you can drop retimers and most DSP, and the faceplate stops being a wall of 12–16 W modules.

Broadcom's March 2024 Bailly disclosure is still the cleanest public accounting. Pluggable optics, the company said, were heading past 50% of switch-system power at 51.2 Tbps and beyond. Bailly's claim was more than 70% lower optical-interconnect power versus standard pluggables, plus an 8× improvement in silicon area efficiency. Later production KPIs, published by Broadcom as TH5-Bailly systems moved from prototype to customer boxes, tightened the number to 5 W per 800 Gbps including the laser, a 60–70% cut versus a traditional DSP transceiver, with transmitter TDECQ consistently under 2 dB.

Those are vendor measurements of the optical interconnect, not independent teardowns of a named hyperscaler SKU, and they are not "the switch uses 70% less power." A Tomahawk 5 still switches 51.2 Tbps of packets. The win is the optics tax.

NVIDIA's version of the same argument is written into the Quantum-X hardware documentation: CPO cuts the high-speed electrical path to a few millimeters inside the substrate, insertion loss to about 4 dB from about 22 dB in a traditional pluggable design, which the company translates as 63× better signal integrity and less DSP. The product-line claim on the silicon photonics page is 5× better power efficiency versus pluggables and higher resiliency (NVIDIA's wording: 10× network resiliency, 5× longer flap-free runtime). Treat the 5× figure as a vendor KPI on a 1.6T-class port, not as a measurement you can drop onto every 800G OSFP in the installed base.

Power per bit is the number people quote and then misuse. 5 W at 800 Gbps is 6.25 pJ/bit for that optical interconnect, if you divide watts by bits per second and ignore FEC, unallocated laser overhead, and the switch ASIC. 14 W at 800 Gbps is 17.5 pJ/bit on the same naive basis. Those pJ/bit figures are derived, not Broadcom's headline. The comparable number in a chiplet PHY is 0.25–0.5 pJ/bit for on-package electrical UCIe — a reminder that CPO is still optics, still lasers, still picojoules, not the sub-picojoule electrical die-to-die. CPO wins against board-plus-module optics. It does not beat copper at 50 mm.

How a CPO package is actually built

A working CPO switch is five problems stacked: the photonic die, the electronic die that drives it, the attach to the switch ASIC, the fiber array, and a laser that can be replaced without scrapping the package.

EIC on PIC, then engines around the ASIC

Silicon photonics gives you modulators, photodetectors, and waveguides on a CMOS-compatible wafer. It does not give you the high-speed drivers and TIAs; those live on an electronic IC, often a finer CMOS node. TSMC's COUPE answer is to stack that EIC directly on the PIC with SoIC-X hybrid bonding so the EIC–PIC interface is bump-less. TSMC's ECTC 2024 paper on COUPE claimed a SoIC-based optical engine offers 23× the bandwidth density of a solder-bump engine on the transmit side, and that lower bond capacitance improves TIA sensitivity enough to cut laser power more than 40%. The 2025 ECTC follow-up reported wafer-level grating-coupler insertion loss on COUPE staying under 1.2 dB, matching the PIC wafer — meaning the 3D stack itself was not adding optical loss after process work.

Those are foundry and conference numbers on test structures, not a guarantee that every NVIDIA or Broadcom engine is a COUPE stack. Broadcom has long built its own SCIP (silicon photonics) engines. NVIDIA's public supply chain for Spectrum-X Ethernet Photonics names TSMC for silicon photonics wafers, SPIL for chip-scale package and test, Lumentum for laser chips, TFC Communication for laser-module subassemblies, and Foxconn for system assembly. That is a CPO manufacturing chain, not a single-vendor miracle.

The engines then sit around the switch die on an organic substrate or a CoWoS-class interposer, the same advanced-packaging complex that already starves AI GPUs of slots. A CPO switch is competing with HBM-equipped accelerators for the same assembly lines. That is a capacity fact, not a metaphor.

Fiber attach is the yield killer

Electrical bumps you can probe. A fiber array unit (FAU) you align to a grating coupler or an edge coupler at micron tolerances, glue, and hope the epoxy and the thermal cycle do not walk. Broadcom's Bailly pitch included "highly automated high-density, edge-coupled fiber attach" and a Broadcom Fiber Connector. NVIDIA's Spectrum-X Photonics materials emphasize a detachable, surface-normal fiber connector attached late in the flow so the photonic package can be tested before fibers go on. Both are admissions that fiber attach, not the Mach–Zehnder, is what kept CPO in the demo tent for a decade.

TSMC has been explicit about the three industrial problems: wafer-level optical test, FAU integration, and high-speed optical package assembly. Until those three yield, "CPO is in production" means a few switch SKUs, not a catalog.

Lasers stay off the package on purpose

A III–V laser does not want to live next to a 1,000 W class switch or GPU die. It wants a controlled temperature and a replacement path. Broadcom's Bailly system was designed around multiple remote laser modules (RLMs). The OIF's companion form factor is ELSFP — External Laser Small Form Factor Pluggable. NVIDIA's Q3450-LD uses 18 removable external light-source modules, one per eight 800G MPO ports, feeding 144 ports. That split — co-packaged engine, pluggable laser — is the 2026 production pattern. On-package lasers exist in research and in some pluggables. They are not how the first AI CPO switches are being serviced.

What actually shipped

Broadcom: Bailly, then 200G/lane

Bailly is the existence proof that a 51.2T CPO Ethernet switch can be a product. Hardware, from the March 2024 customer delivery:

• Broadcom StrataXGS Tomahawk 5, 51.2 Tbps
• Eight 6.4T-FR4 SCIP optical engines with Broadcom Fiber Connector
• 4RU air-cooled system, 128 ports of 400G FR4, 128 duplex LC connectors
• Single-mode fiber from engine to faceplate
• Remote laser modules

Broadcom's own roadmap, presented in 2025, frames three generations: TH4-Humboldt at 25.6T as the first CPO learning vehicle, TH5-Bailly at 51.2T as the volume generation, and a third generation at 200G per lane aimed at 102.4T-class switches (Tomahawk 6 / Davisson in the trade naming). Gen 4, in those slides, is 400G/lane. Treat Gen 3/4 dates as Broadcom's technology leadership claim, not as a purchase order. What is documented is that Bailly exists, that Broadcom has published production-like optical KPIs (5 W/800G, TDECQ < 2 dB), and that the 200G/lane step is how you get to 1.6T ports without doubling the fiber count.

Partners named at the 2024 launch included ByteDance, H3C, Juniper, and Micas — system builders and a cloud operator, not a census of deployed racks. Hyperscaler qualification of CPO is real work: fiber reliability under thermal load, link-flap statistics, and the operational question of whether a dead engine takes down a spine switch. Broadcom and Corning published a joint paper in October 2024 on exactly that fiber-reliability problem. That paper existing is evidence of the failure mode, not of its absence.

NVIDIA: Quantum-X now, Spectrum-X in 2H 2026

NVIDIA split CPO across two fabrics.

Quantum-X InfiniBand Photonics is the one with a hardware user manual. The Q3450-LD is a 4U, liquid-cooled, busbar-powered CPO switch: 144 ports of 800 Gb/s InfiniBand on MPO connectors, 115.2 Tb/s, Quantum-X800 silicon, 200G SerDes. Sister SKUs in the same XDR family (Q3400-RA, Q3401-RD, Q3200-RA) still use OSFP cages; the "-LD" is the co-packaged, liquid-cooled, MPO-faced variant. NVIDIA's stated topology claim is a non-blocking two-level fat tree above 10,000 GPUs. Maximum power in the spec sheet is 4.3 kW for the Q3450-LD with active cables — a whole-box number, not an optics-only KPI. The liquid loops are not optional decoration. A CPO package sitting on a high-radix switch is a direct-to-chip cooling problem.

Spectrum-X Ethernet Photonics is the larger Ethernet bet, built on Spectrum-6, also 200G SerDes. NVIDIA's product page puts total bandwidth at up to 409.6 Tb/s and availability in the second half of 2026. The SN6800-class configuration cited in NVIDIA's engineering blogs is 512 ports of 800 Gb/s (or 2,048 ports of 200 Gb/s) with an in-package fiber shuffle. That is a different scale of faceplate than Bailly's 128×400G. It is also, as of 18 August 2026, a ramp, not an installed-base statistic.

NVIDIA's CPO claims to hold in your head separately from Broadcom's: 3.5× to 5× optical-interconnect power versus pluggables depending on which NVIDIA blog you read (the 3.5× figure appeared with the Quantum-X/Spectrum-X introduction; the 5× figure is attached to Spectrum-X Ethernet Photonics per 1.6T port), 4× fewer lasers than a pluggable equivalent, 10× resiliency. Those are NVIDIA numbers. They are directionally the same story as Bailly's 60–70% optics-power cut. They are not a third-party bake-off.

TSMC: COUPE as the integration layer

TSMC is not selling you a switch. It is selling the way an electrical die and a photonic die become one engine, and the way that engine sits on CoWoS next to a logic die.

The 24 April 2024 North America Technology Symposium wording is the baseline: COUPE uses SoIC-X to stack an electrical die on a photonic die; qualify for small-form-factor pluggables in 2025; integrate into CoWoS as CPO in 2026. The 22 April 2026 symposium updated that to a "true co-packaged optics solution using COUPE on substrate beginning production in 2026," with TSMC's own comparison of 2× power efficiency and 10× latency reduction versus a pluggable on the board, featured on a 200 Gbps micro-ring modulator.

Two timelines are running at once, and mixing them is how COUPE hype happens. The 65 nm silicon-photonics wafer process matured first. The stacked engine, the fiber attach, and the CoWoS-adjacent CPO package are the later, harder product. A micro-ring modulator at 200 Gbps in a foundry talk is a device result. A 409.6T Ethernet switch in a rack is a system. 2026 is the year those two start to share a package. It is not the year every AI GPU grows optical shoreline.

Samsung has said, at OFC 2026, that it is entering silicon photonics with optical engines around 2027 and a turnkey CPO service around 2029. That is a foundry-competition datapoint, not a reason to wait. The assembly capacity that matters in 2026 is still TSMC's, and it is the same CoWoS complex already allocated to HBM GPUs.

1.6T, 3.2T, and 200G per lane

Port speed and switch radix get used interchangeably. They should not be.

• 800G ports on 100G or 200G electrical lanes are what 2026 CPO switches actually terminate. Bailly's faceplate is 128×400G FR4 (the engine is 6.4T; the system breaks it out as 400G). Quantum-X Photonics is 144×800G. Spectrum-X Photonics is specified up to 512×800G.
• 1.6T ports are the next faceplate generation, typically 8×200G optical lanes. They are why 200G/lane CPO (Broadcom Gen 3, NVIDIA's 200G SerDes already) matters. A 1.6T DSP pluggable is a power problem CPO and LPO are both trying to inherit.
• 3.2T in the OIF IA is an engine size (8×400G, 32×112G-XSR), not a port you plug a cable into. Sixteen such engines make a 51.2T switch. Broadcom skipped that grain and built 6.4T engines. Do not read "3.2T CPO" on a slide as "3.2T OSFP."
• 102.4T and 409.6T are switch throughputs. They only work as CPO (or as a faceplate of LPO/DSP modules that the facility cannot cool) because the SerDes count explodes. Copper DAC still wins inside a rack at short reach. The optics argument is scale-out.

A useful heuristic: if the number has a "T" and describes a switch, it is radix × port speed. If it describes a module in an OIF PDF, it is the engine. If it describes a pluggable, it is the cage. Mixing those three is how 3.2T becomes a 2026 product that you cannot buy.

GPU packages versus switch packages

This is the distinction most explainers flatten, including some of NVIDIA's own "optics in the AI factory" language.

A 2026 flagship GPU already has a packaging problem: two reticle-limit dies, eight HBM stacks, a CoWoS interposer, and a copper scale-up fabric (NVLink, UALink-class, Infinity Fabric) inside the rack. Adding a photonic engine to that package means shoreline, thermal isolation from a 1,000-plus-watt die, a fiber escape that does not fight the HBM, and a yield hit on the most expensive SiP in the building. TSMC's COUPE-on-CoWoS work is aimed at that future. IEEE papers on XPU-to-XPU optical links using COUPE are aimed at that future. It is a real direction. It is not how GB200/GB300-class systems get light out of the rack in 2026.

What shipped is CPO on the switch: the box that already had a faceplate full of transceivers. Replacing those transceivers with on-package engines is an optics-and-packaging problem. Replacing NVLink copper with on-GPU optics is an architecture-and-yield problem on top of that. The first one has SKUs. The second has symposium slides.

When UCIe 3.0 added raw-mode mappings for continuous-transmission protocols, co-packaged optics was one of the sockets the consortium had in mind: a photonic engine as a chiplet, talking XSR or raw, not a PCIe function. That is the clean long-term picture — optics as another die in the SiP, next to HBM and the I/O tile. A multi-vendor catalog of those engines is the same "mix and match" problem the chiplet market has not solved for logic. Expect first GPU-adjacent CPO to be single-vendor (the GPU maker's engine, or the foundry's, on that GPU maker's package), not an OIF module you buy from a third party and click onto a Blackwell.

What is real and what is hype

Real

• CPO Ethernet and InfiniBand switches are products in 2026, not only OFC demos. Broadcom delivered 51.2T Bailly in 2024 and has published production optical KPIs. NVIDIA documents the Q3450-LD as a 144×800G liquid-cooled CPO switch; Spectrum-X Ethernet Photonics is on a 2H 2026 availability statement.
• The power argument is physical. Shortening the electrical channel from centimeters to millimeters is why the DSP can go. Broadcom's 5 W/800G (including laser) versus ~14 W/800G DSP pluggable, and NVIDIA's ~4 dB versus ~22 dB insertion-loss comparison, are the two numbers worth keeping.
• External lasers plus co-packaged engines is the production service model. ELSFP/RLM/removable light-source modules exist because operators will not treat a laser as a soldered-down, package-lifetime part.
• TSMC COUPE is a real integration platform with a 2024→2025 pluggable → 2026 CoWoS-CPO roadmap that the 2026 symposium said is entering production. IEEE ECTC papers give device-level evidence (bond density, grating-coupler loss) that the stack can be optically quiet.

Hype

• "CPO is how GPUs talk to each other in 2026." GPUs still scale up over copper and HBM. CPO is how switches talk across the building. Optical XPU I/O is the next packaging fight, not this year's rack BOM.
• "CPO replaces pluggables next year." 400G and 800G DSP and LPO modules remain the volume. CPO is the high-radix AI switch, at a yield and serviceability cost. A campus leaf with 32 ports does not need it.
• "LPO is just CPO in a cage." LPO keeps the board channel and the cage. CPO deletes both. They attack the same DSP watts from opposite ends of the mechanical drawing.
• "5× lower power, so the data center is solved." Optics is a large slice of switch power, not of cluster power. The GPU, the HBM, and the facility cooling still dominate. CPO lets you build a denser fabric. It does not replace a substation.
• "OIF 3.2T means everyone builds the same engine." The IA is a module definition. Broadcom shipped 6.4T engines. NVIDIA built around 200G SerDes and MPO faceplates. Interoperability at the engine footprint is behind interoperability at the fiber.

A realistic timeline

One useful heuristic: ask whether the optical engine is on the switch package or the GPU package, whether the laser is remote, and whether a dead engine is a module swap or a box swap. Do not ask whether the company "has silicon photonics." Everyone serious does.

The bottom line

2026 is the year co-packaged optics stopped being an OFC demo and became a switch you can rack — in a small number of AI fabrics, at a real power saving, with a service model that still treats the laser as a field-replaceable part.

The physics is old. Board traces at 112G and 224G waste watts on DSP. Millimeters of package do not. Silicon photonics is how you build the engine; CPO is where you put it; LPO is how you keep the cage if you cannot live with that placement. Broadcom's Bailly, NVIDIA's Quantum-X Photonics, and TSMC's COUPE-on-CoWoS are three layers of the same stack: a merchant switch, a vertically integrated AI fabric, and a foundry integration service.

For anyone making decisions today, the split is clean. If the question is how a 2026 AI switch gets 800G out of a 4U box without a wall of 14 W modules, you are looking at CPO or at LPO, and the high-radix NVIDIA/Broadcom boxes have chosen CPO. If the question is whether your GPU package will sprout fiber this year, the answer is no — copper and HBM still own the SiP, and light starts at the switch. If the question is whether a vendor's "optical GPU" story is real, ask which package the engine sits on, whether the laser is remote, what the measured W/800G is including the laser, and whether a failed engine is a FRU. Packaging capacity will decide how many of those packages the industry can ship, the same way it already decides HBM and CoWoS.

Frequently asked questions

What is co-packaged optics (CPO)?

CPO is an optical transceiver architecture in which the photonic engine is assembled on the same package as a switch or processor ASIC, so the electrical hop is millimeters of substrate rather than centimeters of board into a QSFP/OSFP cage. Fiber runs from the package to the faceplate. In 2026 production, the laser is usually a separate, replaceable module.

How is CPO different from silicon photonics?

Silicon photonics is the chip technology — waveguides, modulators, detectors on silicon. CPO is the packaging choice of putting a photonic engine next to the logic ASIC. You can build silicon-photonic pluggables (and people do) without doing CPO. You cannot do CPO without some photonic engine, silicon or otherwise.

CPO vs LPO vs pluggable — which should I use?

DSP pluggables if you need reach, multi-vendor spares, and a cage. LPO if you want 30–50% class module-power savings and will still live with a faceplate of OSFPs. CPO if you are building a high-radix AI switch where the faceplate power and SerDes reach are the constraint, and you can accept a different service model. They are not sequential versions of one product.

Does NVIDIA CPO go on the GPU?

Not in the 2026 shipping sense. NVIDIA's CPO products are Quantum-X InfiniBand Photonics and Spectrum-X Ethernet Photonics switches. The GPU still leaves the package over copper and HBM. Optical engines on the GPU CoWoS package are the foundry/roadmap layer (TSMC COUPE), not the SKU.

What is Broadcom Bailly?

Bailly is Broadcom's 51.2 Tbps CPO Ethernet switch platform: a Tomahawk 5 ASIC plus eight 6.4 Tbps FR4 silicon-photonic engines, delivered to customers in March 2024. The public power claim is more than 70% lower optical-interconnect consumption versus standard pluggables; later KPIs cite 5 W per 800 Gbps including laser power.

What is TSMC COUPE?

Compact Universal Photonic Engine. TSMC stacks an electrical IC on a photonic IC with SoIC-X and then, in the 2026 production flow, puts that engine on a substrate/CoWoS package as CPO. It is a foundry integration platform used by switch and, later, XPU customers. It is not a transceiver brand.

Why not keep the lasers on the package too?

Lasers are temperature-sensitive, wear out, and are the part operators expect to replace. Production CPO designs (Broadcom RLM, OIF ELSFP, NVIDIA's 18 removable light sources on the Q3450-LD) keep them off the ASIC package so a laser failure is a module swap, not a switch RMA.

When will 1.6T and 3.2T CPO be common?

1.6T is the next port speed, tied to 200G optical lanes; CPO and LPO will both show up there in the late 2020s as 800G DSP modules run out of power. 3.2T in OIF documents is mostly an engine granularity for 51.2T switches, already outpaced by Broadcom's 6.4T engines. A 3.2T faceplate port is a later generation. Do not plan a 2026 BOM around it.

Methodology

This guide is based on primary vendor, foundry, and standards disclosures available as of 18 August 2026: Broadcom's 14 March 2024 Bailly customer-delivery release (eight 6.4T SCIP engines, Tomahawk 5, 70% optical-interconnect power claim, 8× silicon-area efficiency, 4RU 128×400G FR4, remote laser modules); Broadcom's subsequent TH5-Bailly production KPIs (5 W optical interconnect per 800 Gbps including laser, 60–70% versus DSP pluggables, TDECQ < 2 dB); the OIF Implementation Agreement OIF-Co-Packaging-3.2T-Module-01.0 (3.2T engine, 32× CEI-112G-XSR, 8×400G FR4/DR4, ~140 G/mm, targeting 16 engines around a 51.2T switch, plus ELSFP as the external-laser companion); NVIDIA's silicon photonics product page (Quantum-X InfiniBand Photonics, Spectrum-X Ethernet Photonics up to 409.6 Tb/s available 2H 2026, 200G SerDes, 5× power-efficiency claim) and the Q32xx/Q34xx XDR hardware manual (Q3450-LD: 144×800G MPO, 115.2 Tb/s, 4U liquid-cooled, 4.3 kW max, ~4 dB vs ~22 dB insertion loss); TSMC's 24 April 2024 North America Technology Symposium release (COUPE, SoIC-X EIC-on-PIC, pluggables 2025, CoWoS CPO 2026) and 22 April 2026 symposium release (COUPE-on-substrate production in 2026, 2× power and 10× latency versus board-level pluggable, 200 Gbps micro-ring modulator); TSMC/IEEE ECTC 2024 COUPE paper (23× Tx bandwidth density vs solder-bump engines; >40% laser-power reduction via TIA sensitivity) and ECTC 2025 characterization (grating-coupler IL < 1.2 dB on COUPE). pJ/bit figures of 6.25 and 17.5 are derived from Broadcom's 5 W and ~14 W per 800 Gbps KPIs and are labeled as such; they are not vendor-published energy/bit specs. NVIDIA's 3.5× and 5× power-reduction figures are both company claims from different product write-ups and are not treated here as a single measured ratio. Unit-shipment counts for Bailly that appear only in secondary market notes are omitted.