Silicon Photonics: A Full Guide to the Optical Chips Moving AI Data

Silicon photonics is not a synonym for co-packaged optics, and it is not a photonic computer. It is a chip platform: waveguides, modulators, and detectors patterned on silicon so data can leave an electrical SerDes as light. Pluggable 800G modules, CPO switch engines, and optical I/O chiplets all draw from that platform. Confusing the materials with the packaging choice is how a roadmap slide gets treated like a bill of materials.

That distinction matters in 2026 because AI fabrics are forcing optics closer to silicon. Board traces at 112G and 224G SerDes rates burn watts on equalization. Faceplates fill with modules that can eat half a switch's power budget. Copper still wins the short, hot path inside an NVLink-class rack. Light wins when reach and beachfront density make the electrical hop the expensive part. The useful question is which silicon-photonic product form you are buying, not whether a vendor "has silicon photonics."

This guide covers the device stack, the three product forms shipping or approaching volume, the foundries that matter, and an honest timeline for light on the GPU package. Optical engines sitting on switch packages are covered in depth in the co-packaged optics full guide. How GPUs talk inside a domain versus across a hall is in the NVLink, InfiniBand, and UALink guide. Packaging capacity for the engines sits in the same CoWoS and hybrid-bonding world as HBM GPUs.

Key takeaways

• Silicon photonics is the chip technology. CPO is a placement decision. You can ship silicon-photonic pluggables for years without putting an engine on the ASIC package. You cannot do CPO without some photonic engine.
• Volume proof already exists in pluggables. Intel's silicon photonics page states more than 8 million photonic integrated circuits (PICs) and more than 32 million on-chip lasers shipped since 2016 inside data-center transceiver modules.
• Three product forms share one platform. (1) DSP or linear pluggable modules, (2) co-packaged engines on switch ASICs, (3) optical I/O chiplets aimed at XPUs. Only the first is commodity volume in 2026. The second has named switch SKUs. The third is test silicon and funded roadmaps.
• Foundries are the scarce layer. GlobalFoundries' Fotonix platform monolithically combines 300 mm photonics with 300 GHz-class RF-CMOS. TSMC's COUPE stacks an electrical IC on a photonic IC with SoIC-X. Intel runs a high-volume hybrid laser-on-wafer flow for its own PICs.
• Optical I/O chiplets are raising real money against a 2028 volume window. Ayar Labs closed a $500 million Series E on 3 March 2026 (total funding $870 million, $3.75 billion valuation) to scale production of its TeraPHY engines, including an 8 Tbps UCIe-class optical chiplet powered by a 16-wavelength SuperNova light source.
• Lasers remain the awkward part. Efficient electrically pumped lasers are III-V devices, not native silicon. Production CPO often keeps lasers remote. Intel's OCI path integrates on-chip DWDM lasers. Different products make different serviceability bets.
• GPU-package light is not the 2026 default BOM. Scale-up inside NVL72-class racks is still copper. Optical shoreline on the accelerator package is the next packaging fight, not this year's rack wiring diagram.

Silicon photonics at a glance

What silicon photonics actually is

Start with the wafer. A silicon-on-insulator (SOI) photonic process patterns a thin silicon layer into waveguides that confine infrared light by refractive-index contrast. Those waveguides route light across the chip the way metal routes electrons, with bends, splitters, filters, and couplers instead of vias and traces.

A photonic integrated circuit (PIC) holds the optical devices. An electronic integrated circuit (EIC) usually holds the high-speed drivers and transimpedance amplifiers. Some platforms, notably GlobalFoundries Fotonix, push toward monolithic photonics plus RF-CMOS on one die. Others, notably TSMC COUPE, stack a finer-node EIC onto a photonic die with hybrid bonding. Both are silicon photonics. They are different manufacturing bets.

What the platform does not do by itself is invent a new algorithm. Light carries bits. Matrix multiplies still happen in transistors (or in specialty analog photonic processors that are a different product category and not this guide). Inside Deep Tech treats "silicon photonics for AI" as interconnect first, computing second, because that is where the shipping volume and the power math are.

Building blocks: waveguides, modulators, detectors, lasers

Waveguides and couplers

Silicon and silicon-nitride waveguides carry the light. Edge couplers and grating couplers get it on and off the chip into fiber. Fiber attach is a manufacturing problem as much as a physics problem: micron alignment, epoxy stability, thermal cycling, and wafer-level optical test. That is why detachable connectors and passive V-grooves show up in foundry decks. A beautiful modulator that cannot be fiber-attached at yield is a lab sample.

Modulators: Mach-Zehnder versus micro-ring

Two modulator families dominate datacom silicon photonics.

Mach-Zehnder modulators (MZMs) split light into two arms, phase-shift one or both, and recombine. They are larger, more thermally stable, and more linear. That makes them forgiving in manufacturing and in PAM4 links. Conference device papers in 300 mm CMOS silicon-photonics flows have shown roughly 60 GHz electro-optic bandwidth class MZMs aimed at 200 Gbps PAM4, and compact MZMs pushing toward higher baud. Those are device results, not a guarantee every module uses that exact design.

Micro-ring modulators are tiny resonant devices. They win on footprint and on dense wavelength-division multiplexing, because many rings can sit on one bus waveguide. They lose on thermal sensitivity: the resonance drifts with temperature, so you need heaters, control loops, and margin. Public 200G-per-wavelength ring papers report electro-optic bandwidths in the mid-tens of GHz depending on drive swing and operating point. Rings are why DWDM optical I/O pitches look dense on a slide. They are also why thermal control is a first-class part of the product, not an afterthought.

Germanium photodetectors

Silicon is an awkward absorber at O-band datacom wavelengths, so receivers typically use germanium photodetectors integrated on the PIC. The Ge PD plus a TIA on the EIC turns light back into a clean enough electrical eye for the SerDes. Detector speed and responsivity set how hard the laser and the link budget have to work.

The laser problem

Silicon does not make a great electrically pumped laser. Efficient gain lives in III-V materials. The industry's answers are not interchangeable:

• Hybrid laser-on-wafer. Intel's public silicon photonics story emphasizes wafer-scale hybrid lasers with direct coupling, enabling wafer-level test and burn-in, and cites tens of millions of on-chip lasers shipped in pluggables.
• External or remote lasers. Production CPO switches often keep the laser in a replaceable module and feed light into co-packaged engines. Serviceability beats integration purity when the ASIC package costs as much as a car.
• Heterogeneous / quantum-dot paths. Research and specialty flows keep trying to put better light sources closer to the PIC. Treat aggressive on-package laser claims as architecture choices that need a failure-and-replace story.

If a vendor says "fully integrated optics," ask where the laser lives and what happens when it dies.

Three product forms that share one platform

Pluggables are how silicon photonics paid the bills. Intel's own overview frames its platform as field-proven in transceiver modules, with Optical Compute Interconnect (OCI) as the chiplet-class next step: a PIC plus advanced-node CMOS EIC stack with on-chip DWDM lasers and SOAs, first-generation bandwidth at 4 Tbps bidirectional, standard SMF-28 fiber, and a design target of co-packaging with CPUs, GPUs, IPUs, and other SoCs. That is a primary-source product thesis, not a third-party market model.

CPO is where the engine moves onto the switch package so the board channel shrinks. Power KPIs, Bailly, Quantum-X Photonics, Spectrum-X Photonics, and TSMC COUPE production language belong in the CPO full guide. The short version for this page: CPO uses silicon photonics. Silicon photonics does not require CPO.

Optical I/O chiplets are the form factor AI scale-up architects care about when copper beachfront runs out. Ayar Labs' TeraPHY line is the clearest public example as of September 2026: an optical engine family pitched for AI scale-up, including what the company called the first UCIe optical interconnect chiplet at 8 Tbps class bandwidth, driven by a 16-wavelength SuperNova light source. Public technical descriptions break that into eight 1 Tbps-class optical ports and multi-wavelength fibers. On 3 March 2026 the company announced a $500 million Series E to accelerate volume production and test capacity, bringing total funding to $870 million at a $3.75 billion valuation. Company and press timing points volume ramps at customer AI systems in the 2028 window. That is a funding and roadmap signal, not a hall full of shipping GPU packages today.

Foundries and who actually builds the wafers

Operators do not buy "photonics." They buy modules, switches, and eventually packages that someone could yield. Three manufacturing stories dominate public AI interconnect talk.

Intel: volume PICs and OCI

Intel positions itself as a volume silicon-photonics manufacturer with U.S. fab flow, hybrid lasers, and a transceiver-component portfolio spanning 400G, 800G, and 1.6T class designs. The shipment counts above are the credibility claim. OCI is the co-packaged compute-interconnect claim: integrated lasers on the PIC side, no external laser required in that architecture, detachable optical connector on the roadmap, evaluation platforms for partners. Read Intel's numbers as Intel's. They still matter because few other vendors publish on-chip laser shipment totals in the tens of millions.

GlobalFoundries Fotonix: monolithic CMOS + photonics

GF Fotonix is a 300 mm monolithic platform that combines photonic devices with 300 GHz-class RF-CMOS. GF's launch materials claimed 0.5 Tbps per fiber class performance enabling 1.6–3.2 Tbps optical chiplets, and later GF technology pages describe support for 100–200 G per wavelength depending on generation, with device libraries in the 56–112 Gbaud class. The architectural pitch is consolidation: photonics, RF, and logic features that used to be split across chips. Ayar Labs has publicly tied early TeraPHY silicon to GF's 45SPCLO / Fotonix lineage while also working TSMC packaging paths for stacked engines. Foundry choice and packaging choice are no longer the same decision.

TSMC COUPE: stack the EIC on the PIC

TSMC's Compact Universal Photonic Engine uses SoIC-X hybrid bonding to put an electrical die on a photonic die, then brings that engine into CoWoS-class CPO flows. That is why COUPE shows up next to hybrid bonding and CoWoS in the same capacity conversation as HBM GPUs. A CPO engine and an HBM stack compete for advanced packaging slots. Silicon photonics does not escape the packaging bottleneck just because the bits are optical.

Standards shoreline: UCIe

Optical I/O as a chiplet wants a die-to-die electrical standard measured in millimeters, then fiber for the rest of the journey. That is why UCIe raw-mode and optical-chiplet announcements matter together. The electrical standard is covered in the chiplets and UCIe guide. Silicon photonics is what turns that short electrical hop into a rack-scale or row-scale optical hop without another power-hungry long-reach SerDes.

Why AI cares now

AI did not invent silicon photonics. Hyperscale pluggables did. What changed is the shape of the power and density problem.

Inside a rack-scale NVLink domain, copper and HBM still dominate for good reasons: latency, energy per bit at tens of millimeters, and a mature packaging playbook. Across racks and halls, 800G and 1.6T optics are how gradients, experts, and KV cache move. When the electrical channel from ASIC to cage becomes the tax, you either starve the module DSP (LPO), delete the cage (CPO), or eventually put an optical chiplet on the compute package itself.

Beachfront density is the quieter constraint. Reticle-limited XPUs already spend shoreline on HBM. Every SerDes lane you keep electrical is shoreline and watts you cannot spend elsewhere. Multi-wavelength optical ports are how vendors argue for more bits per millimeter of package edge. That argument only works if fiber attach, lasers, and thermal isolation work at the yield of a $30,000-plus SiP.

What is real and what is hype

Real

• Silicon-photonic pluggables are a volume industry with multi-million PIC shipment claims from at least one major supplier.
• CPO switches in 2026 use silicon-photonic engines; the packaging and power story is documented in primary vendor materials summarized in the CPO guide.
• Monolithic (GF) and 3D-stacked (TSMC COUPE) foundry platforms are shipping or entering production flows for AI interconnect customers.
• Optical I/O startups are raising late-stage capital against named bandwidth targets (8 Tbps-class UCIe chiplets) and a late-decade volume window.

Hype

• "Silicon photonics replaces copper in 2026 AI racks." Copper still owns scale-up domains. Optics owns scale-out and is invading the switch package first.
• "CPO and silicon photonics are the same announcement." One is packaging. One is devices.
• "On-chip lasers everywhere." Many production CPO designs keep lasers remote on purpose.
• "Market will be $X billion by 2030." Secondary market PDFs disagree with each other by multiples. This guide does not launder those figures into facts.

A realistic timeline

The bottom line

2026 is the year silicon photonics stopped needing a science fair to justify itself in AI infrastructure conversations. The platform already ships in millions of pluggable PICs. It already sits on CPO switch packages. It is now trying to earn a seat on the accelerator package itself.

Inside Deep Tech's take: buy the product form, not the buzzword. If you need ports you can swap, you are in pluggables (DSP or LPO). If you are building a high-radix AI switch and the faceplate is the thermal wall, you are in CPO, and silicon photonics is how the engine is built. If you are planning XPU optical shoreline, you are funding packaging risk, laser strategy, and UCIe-class attach against a late-decade volume bet. The named downside is blunt: optical I/O that fails fiber attach or laser serviceability on a CoWoS-class package is not a transceiver RMA. It is a scrap event on the most expensive assembly line in the building.

Ask four questions of any silicon-photonics pitch. Where does the engine sit? Where does the laser sit? What is the measured energy and reach including the light source? What is the field-replaceable unit when something goes dark? Vendors that answer those cleanly are doing interconnect engineering. Vendors that only say "light is the future" are doing slides.

Frequently asked questions

What is silicon photonics?

A semiconductor platform that builds optical waveguides, modulators, and detectors on silicon wafers, usually paired with electronics for drive and receive, so high-speed links can run over fiber.

How is silicon photonics different from CPO?

Silicon photonics is the chip technology. Co-packaged optics is the decision to put a photonic engine on the same package as a switch or processor ASIC. See the CPO guide.

Is silicon photonics already in data centers?

Yes. Silicon-photonic pluggable modules have been shipping into hyperscale networks for years. Intel alone cites more than 8 million PICs shipped since 2016.

Will optical I/O replace NVLink copper in 2026?

No. NVLink-class scale-up inside dense racks remains copper-dominated in 2026. Optical I/O is aimed at extending high-bandwidth links beyond copper's sweet spot. See the GPU interconnect guide.

What is Ayar Labs TeraPHY?

An optical engine / chiplet product line for AI scale-up interconnect, including an 8 Tbps-class UCIe optical chiplet with a multi-wavelength SuperNova light source. The company raised a $500 million Series E in March 2026 to scale production.

What is GF Fotonix?

GlobalFoundries' 300 mm monolithic silicon-photonics platform combining photonic devices with high-speed RF-CMOS features for optical interconnect chips and chiplets.

What is TSMC COUPE?

Compact Universal Photonic Engine: TSMC's approach to stacking an electrical IC on a photonic IC (SoIC-X) and integrating that engine into advanced packages for CPO.

Why aren't lasers just built in silicon?

Efficient laser gain typically requires III-V semiconductors. Silicon photonics integrates or attaches those sources, or keeps them in external modules for serviceability.

Methodology

Primary sources as of 2 September 2026: Intel Silicon Photonics overview (8M+ PICs, 32M+ on-chip lasers since 2016; OCI 4 Tbps bidirectional chiplet with on-chip DWDM lasers/SOAs; SMF-28; co-package targets); GlobalFoundries Fotonix announcement and GF silicon-photonics technology pages (monolithic 300 mm photonics + 300 GHz-class RF-CMOS; 0.5 Tbps/fiber class claim; 100–200 G/λ generational language); Ayar Labs 3 March 2026 Series E release ($500M, $870M total funding, $3.75B valuation) plus Ayar's public UCIe TeraPHY / SuperNova product descriptions (8 Tbps-class optical chiplet, 16-wavelength light source). CPO switch KPIs and COUPE production details are summarized from the site's CPO full guide rather than re-derived here. Modulator bandwidth figures cited as conference device results, not module SKUs. Secondary market-size forecasts were reviewed and intentionally omitted because published 2026–2034 totals disagree by large multiples.