RISC-V for AI: A Full Guide to Open ISA Silicon When Proprietary Cores Are Not Enough
RVA23 (Oct 2024) makes Vector and Hypervisor mandatory. This guide covers RISC-V AI hosts and NPUs in 2026: SiFive, Tenstorrent, Andes/Axelera, NVIDIA's cores, matrix extensions, software gates, and honest limits versus Arm and x86.
Arm and x86 still run most of the hosts that schedule AI jobs. The question for 2026 is not whether those ISAs disappear. It is whether AI silicon teams can keep shipping differentiated NPUs, vector CPUs, and chiplet hosts while renting their instruction set from a single proprietary licensor.
This guide covers what RISC-V actually is in the AI stack, why the RVA23 profile matters more than marketing slides, how vector and matrix extensions map to transformers, who is shipping or sampling AI-relevant silicon (SiFive, Tenstorrent, Andes, Axelera, NVIDIA's own cores, and others), how software (Linux, CUDA/ROCm ports, PyTorch) is catching up, and the honest limits that keep Arm Neoverse and x86 EPYC on the same BOM.
Key Takeaways
- RVA23 (ratified 21 Oct 2024) makes Vector and Hypervisor mandatory for portable application-class RISC-V.
- 2026 is the first year of RVA23-class server and AI host silicon, not a finished fleet replacement for Arm/x86.
- AI value sits in custom extensions and NPUs on top of RISC-V, not in the base ISA alone.
- Matrix task groups (IME, VME, AME) are still standardizing; do not treat them as one ratified AI matrix ISA yet.
- Open ISA is not open silicon: IP cores, toolchains, and packaging still decide who ships.
What RISC-V actually is in an AI system
RISC-V is an open instruction set architecture. Companies implement cores under a permissive license from RISC-V International instead of paying Arm Architecture License fees for every custom SoC. The ISA is modular: a vendor can ship a tiny microcontroller core or a 64-bit out-of-order server core from the same family of standards.
In AI systems, RISC-V shows up in three places that get conflated in press releases.
- Host / head-node CPUs that boot Linux, schedule workers, and talk to GPUs or XPUs over PCIe or a coherent fabric.
- Control and pre/post processors next to a proprietary NPU or tensor engine (vision pipelines, tokenization, KV-cache staging).
- Domain-specific accelerators that keep a RISC-V front-end while the heavy FLOPs run on custom matrix hardware.
Here's why that split matters. Buying "RISC-V AI" as a slogan tells you almost nothing about whether you get a CUDA-host substitute, an edge vision AIPU, or an IP core you still have to tape out. Inside Deep Tech's chiplets and UCIe full guide is the right companion when the product is a multi-die package rather than a single core.
Why RVA23 is the real 2026 inflection
Profiles are how RISC-V turns a cafeteria of extensions into a binary target. On 21 October 2024, RISC-V International announced ratification of RVA23. For application processors that run rich OS stacks, RVA23 makes the Vector extension and the Hypervisor extension mandatory, alongside other baseline features needed for modern Linux distributions.
That sounds bureaucratic. It is not. Without a shared profile, every Linux distro and every AI framework had to guess which extensions a board actually implemented. With RVA23, Canonical can require the profile as a floor. Ubuntu 25.10 moved to RVA23, and Ubuntu 26.04 LTS carries that requirement into long-term support, while Ubuntu 24.04 LTS remains available for older RVA20 hardware.
EE Times coverage of RISC-V Summit Europe 2026 in Bologna framed 2026 as the year of RVA silicon for data centers: the Server Platform Specification 1.0 sits on RVA23, and SiFive's Krste Asanović said hyperscalers and data-center owners are designing next-generation processors around the open ISA's flexibility and business model.
Inside Deep Tech's take on the date stamp: RVA23 is necessary but not sufficient. It is the ABI contract that lets software vendors stop forking. It does not by itself deliver Neoverse-class single-thread performance, NVLink-coherent GPU hosts, or a sold-out CoWoS allocation.
Vector, matrix, and why transformers care
The "V" in RISC-V has always gestured at vectors. Ratified RVV (RISC-V Vector) gives flexible vector lengths and mixed-precision friendly math that maps cleaner to ML kernels than fixed-width SIMD bolted onto a general-purpose core. RVA23 makes that vector baseline mandatory for application-class chips.
Transformers still live on matrix multiplies. RISC-V International's AI Market Development Committee describes three matrix-oriented task groups: Integrated Matrix Extension (IME), Matrix-in-Vector Extension (VME), and Attached Matrix Extension (AME). The point of the open process is evidence-driven instructions with LLVM/GCC and framework support upstreamed before silicon ships.
Do not confuse those drafts with a finished, single AI matrix ISA. As of September 2026, vendors still ship proprietary tensor units (Semidynamics Tensor Unit, Axelera D-IMC arrays, Tenstorrent datapaths) while contributing to the shared extensions. Portability across vendors will follow ratification and profile uptake, not press-release acronyms.
| Layer | What it is | AI role in 2026 | Maturity |
|---|---|---|---|
| RVA23 profile | Mandatory Vector + Hypervisor application baseline | Portable Linux / Android ABI target | Ratified Oct 2024; silicon ramping 2026 |
| RVV vectors | Scalable vector ISA | Quantized inference, DSP-like kernels | Deployed; llama.cpp and compilers use it |
| IME / VME / AME | Matrix extension task groups | Standardize GEMM-class ops | In progress; not one ratified matrix ISA yet |
| Custom NPU / tensor | Vendor-specific accelerators | Most of the TOPS on edge AI SoCs | Shipping; software is vendor-coupled |
| Server Platform Spec 1.0 | Data-center platform on RVA23 | Enterprise OS and firmware expectations | Announced; early platforms |
Who is actually shipping AI-relevant RISC-V silicon
The commercial map is denser than it was in 2024, and still thinner than Arm's Neoverse ecosystem.
SiFive: IP plus a server that sells time
SiFive, founded by RISC-V inventors, sells Performance and Intelligence CPU IP and has put a development server (BigSky) in customers' hands so teams can port Linux, CUDA head-node paths, and ROCm before their own SoC tapes out. In 2026 SiFive announced a $400 million financing at a $3.65 billion valuation, with NVIDIA among the investors, aimed at data-center and AI infrastructure IP. Management positions the P870-D as competitive with Arm Neoverse N2-class cores and has a fourth-generation Performance IP line in flight for the top of the data-center stack.
The business model caveat is structural. An IP licensor funding a server is buying software gravity. The return shows up when BigSky porting converts into licensed custom SoCs, not when a 2U box wins a production GPU cluster.
Tenstorrent, Andes, Axelera, and the edge-to-rack spread
Tenstorrent builds AI processors with RISC-V CPU cores and chiplets, and has opened chiplet specs (OCA) for composable systems. Andes, a founding RISC-V International member, supplies cores across edge-to-server ranges; on 1 June 2026 it announced that Axelera AI integrated AndesCore AX65 into the Europa AIPU for control next to Axelera's Digital In-Memory Compute fabric.
Axelera's Europa generation is a concrete edge number, not a slogan: EE Times reports 629 TOPS (INT8), eight AI cores versus Metis, RISC-V vector clusters for pre/post processing, samples targeted for Q2 2026, and a $250 million round that the company called the largest EU AI-chip raise of its kind. Europa is still an edge/server-adjacent AIPU, not a Blackwell substitute.
NVIDIA and the "RISC-V everywhere except the FLOPs" pattern
NVIDIA has shipped RISC-V cores at enormous unit volume inside its platforms (RISC-V International cited over 1 billion RISC-V cores shipped by NVIDIA in 2024) and has publicly committed to bringing CUDA orchestration to RVA23 hosts. That is strategically important and easy to overread. It validates RISC-V as the control and host layer around proprietary GPU datapaths. It does not mean the tensor cores themselves became an open ISA.
For how those GPUs talk at scale-up and scale-out, use Inside Deep Tech's NVLink, InfiniBand, and UALink guide. RISC-V hosts still need a coherent story for packaging and HBM when they sit next to accelerators; see the TSMC CoWoS full guide and the HBM full guide.
| Vendor / program | Role | 2026 signal | What it is not |
|---|---|---|---|
| SiFive Performance / BigSky | CPU IP + RVA23 server platform | $400M round; CUDA/ROCm head-node demos | A volume hyperscaler CPU SKU yet |
| Tenstorrent | AI processors + RISC-V cores + chiplets | Inference systems; open chiplet specs | A drop-in CUDA training GPU |
| Andes + Axelera Europa | RISC-V control + D-IMC AIPU | 629 TOPS INT8; AX65; samples Q2 2026 | Data-center training silicon |
| NVIDIA RISC-V cores | Control / platform CPUs at huge volume | CUDA→RVA23 pledge; >1B cores (2024) | Open GPU datapath |
| Qualcomm + Ventana | Data-center RISC-V CPU roadmap | Ventana acquisition into Dragonfly path | Shipping fleet displacement of Arm |
Software: the real gating item after RVA23
Hardware without distributions is a lab demo. The 2026 story is that enterprise Linux finally has a profile to target. Red Hat's RHEL 10 developer preview path on SiFive platforms, Canonical's RVA23 requirement, and upstream work through the RISE project on PyTorch and related frameworks are how an open ISA becomes an operable platform.
AI frameworks still trail x86/Arm maturity. Quantized inference paths (llama.cpp on 128-bit vectors) prove kernels can move. Full training stacks, multi-node collectives, and day-one CUDA feature parity on a RISC-V host are still engineering programs, not checked boxes. Treat "CUDA on RISC-V" announcements as head-node and orchestration milestones unless the vendor publishes a training benchmark you can reproduce.
RISC-V versus Arm and x86 for AI hosts
A fair comparison is not "open versus closed" as a moral claim. It is three columns: licensing and customization, software maturity, and system integration with accelerators.
Arm Neoverse wins today on shipping GPU-host platforms with coherent attach stories (Grace, Vera-class roadmaps) and a deep ISV catalog. x86 wins on default enterprise ops muscle. RISC-V wins when a team needs to own custom instructions, avoid a single ISA licensor, or meet a sovereignty mandate that treats proprietary ISA roadmaps as a supply risk.
Omdia figures cited by RISC-V International put the global AI processor market at $261.4 billion in 2025, growing to $385.4 billion by 2030 at an 8.1% CAGR, with hardware still roughly 70% of revenue. That scale is why every ISA wants an AI narrative. It is also why buyers should separate "AI processor market" slides from "RVA23 server SKU you can order with HBM and a supported distro."
On the flip side, RISC-V's modularity is a double-edged tool. The same freedom that lets Semidynamics or Axelera tune tensor paths lets vendors diverge enough that binary AI wheels break. Profiles and upstream co-design are the industry's answer. Diligence is still required on which extensions are profile-mandatory versus vendor-private.
Chiplet economics and why the ISA is only one BOM line
Most serious AI RISC-V stories in 2026 are chiplet stories. Tenstorrent's open chiplet approach, Ventana-class modular CPUs, and Axelera's path to Titania chiplets all assume die-to-die links and advanced packaging. The ISA decides what software you can compile. Packaging and memory decide whether the part exists.
That means a RISC-V AI diligence checklist has to look like an accelerator checklist: foundry node, base-die or IO-die plan, HBM versus LPDDR versus on-chip SRAM, thermal envelope, and OSAT or CoWoS slot. Teams that stop at "we licensed a core" discover the hard parts later.
Honest limits (read these before a design win slide)
- Open ISA ≠ commodity CPU. You still buy or design IP, PHY, HBM attach, and a thermal solution.
- Custom instructions create performance and also fragment binaries if they escape carefully versioned libraries.
- Matrix extensions are not finished standards. Vendor tensor units remain the TOPS source on most AI SoCs.
- Arm Neoverse and x86 still own mature GPU-host coherency stories (Grace/Vera-class, EPYC) in volume.
- Physical AI robots and edge vision can adopt RISC-V faster than hyperscaler training hosts. That is a workload fact, not a failure of the ISA. See the September 2026 Physical AI Market Report.
How to evaluate a RISC-V AI claim in diligence
Ask these questions in order:
- Is the part RVA23 (or a named profile) compliant, or only "RISC-V inspired"?
- Where do the FLOPs live: RVV, a ratified matrix extension, or a proprietary NPU?
- Which OS images boot without a vendor fork, and for how long are they supported?
- What is the packaging path (organic, CoWoS-class, chiplet) and who owns HBM or LPDDR allocation?
- Is the demo a head-node for someone else's GPU, or a measured end-to-end model?
FAQ
What is RISC-V in plain terms?
RISC-V is an open instruction set architecture. Chip designers implement compatible CPU cores without licensing a proprietary ISA from Arm or x86 vendors. The openness is about the instruction definitions and the standards process, not about giving away finished silicon.
What is RVA23 and why does it matter for AI?
RVA23 is the ratified 2024 application-class profile that makes Vector and Hypervisor extensions mandatory for portable 64-bit RISC-V processors running rich OS stacks. AI teams care because Linux distributions, Android ABI work, and framework builds need a stable binary target before they invest in optimization.
Will RISC-V replace Arm in AI data centers?
Not as a wholesale swap in 2026. RISC-V is entering server and AI-host sockets through IP wins, development platforms, and sovereign or custom SoC programs. Arm Neoverse and x86 still dominate shipping GPU-host fleets. The credible path is coexistence and selective displacement where customization or licensing flexibility wins.
How does RISC-V help AI accelerators specifically?
Teams can add vector and custom matrix or NPU paths without waiting on a proprietary ISA roadmap, then keep a standard RVA23 baseline for Linux and tooling. That helps edge AIPUs and custom inference silicon more immediately than it helps frontier training GPUs.
Is CUDA available on RISC-V?
NVIDIA has committed to CUDA support targeting RVA23 hosts, and SiFive has shown CUDA used in head-node roles on its server platform. Treat that as orchestration and host enablement unless you have a published training benchmark for your exact model and interconnect.
Who are the main RISC-V AI silicon players in 2026?
SiFive (CPU IP and platforms), Tenstorrent (AI processors with RISC-V cores), Andes (core IP), Axelera (edge AIPUs with RISC-V control), Alibaba/XuanTie, Semidynamics, and large platform vendors that ship RISC-V control cores at volume, including NVIDIA. Qualcomm's Ventana-related roadmap is part of the data-center CPU race.
What should buyers watch next?
Named hyperscaler SoC tape-outs on RVA23 IP, ratification progress on matrix extensions, Linux package parity versus Arm/x86, and whether CUDA/ROCm head-node demos turn into reproducible multi-node jobs. Pin-speed and TOPS slides without a packaging and software plan are incomplete.
RISC-V will not erase proprietary ISAs from the AI rack this year. It will decide, for a growing set of custom and edge designs, whether the control plane and the extension surface stay negotiable. That is the procurement question that matters on Monday: not "is RISC-V real," but "which profile, which FLOPs engine, and which software image ship with the part."
