> ## Content Index > Fetch the complete content index at: https://www.insidedeeptech.com/llms.txt > Use this file to discover other available public pages before exploring further. # Optical I/O: A Full Guide to Chip-to-Chip Photonics When Copper Scale-Up Runs Out of Reach - URL: https://www.insidedeeptech.com/optical-io-chip-to-chip-photonics-ai-full-guide/ - Published: 2026-09-21T06:15:08.000Z - Updated: 2026-09-21T06:15:08.000Z - Description: Optical I/O for AI scale-up: Ayar Labs 8 Tbps UCIe TeraPHY, Intel 4 Tbps OCI, Marvell/Celestial Photonic Fabric (Feb 2026), and honest limits versus CPO, LPO, and copper UALink/NVLink. - Author: Austin Heaton - Tags: AI, Hardware, Semiconductors Copper still wins the densest single-rack AI pods. Past about a meter at 200G-class rates, the scale-up problem stops being a serdes problem and becomes a photonics packaging problem. This guide covers **Optical I/O**: chip-to-chip and co-packaged photonic engines that attach beside XPUs over standards like UCIe, push multi-terabit links over single-mode fiber, and sit between electrical scale-up fabrics and switch-side co-packaged optics. You will get the architecture, the 2024 to 2026 primary milestones from Ayar Labs, Intel, and Marvell/Celestial AI, how Optical I/O differs from silicon photonics device primers and from CPO/LPO, and the honest limits that keep most 2026 BOMs on copper inside the rack. ## Key Takeaways - Optical I/O puts photonic engines next to XPUs so scale-up can leave the copper meter-scale wall. - Ayar Labs TeraPHY is a UCIe optical retimer chiplet claiming 8 Tbps bidirectional bandwidth. - Intel OCI demoed 4 Tbps bidirectional at OFC 2024 at about 5 pJ/bit versus \~15 pJ/bit pluggables. - Marvell closed Celestial AI on Feb 2, 2026, folding Photonic Fabric into its Data Center Group. - Optical I/O is not CPO, not LPO, and not volume GPU copper replacement in most 2026 racks. 📌 Scope note: Optical I/O here means co-packaged or near-package photonic chiplet engines for chip-to-chip and rack-to-rack scale-up (UCIe-class attach, DWDM fiber, external or on-chip lasers). It is not a glossary for silicon photonics process tech alone, not switch CPO cages, and not DSP-less LPO pluggables. Claims are dated as of September 2026 and cite vendor primary releases, Hot Chips materials, and company newsrooms. Do not invent shipping SKU dates vendors have not published. ## What Optical I/O actually is Optical I/O is the practice of moving high-bandwidth traffic on and off a compute package with light instead of long electrical traces or pluggable front-panel modules. In the AI scale-up framing used by Ayar Labs and Intel, a photonic chiplet (or stacked PIC plus EIC) sits in the same multi-chip package as the XPU, speaks a short-reach die-to-die electrical interface such as **UCIe**, retimes or serializes that traffic, and launches DWDM wavelengths onto single-mode fiber. Here's why that framing matters. Operators already buy three related but different photonics stories. [Silicon photonics](https://www.insidedeeptech.com/silicon-photonics-ai-data-centers-full-guide/) is the device and foundry layer (waveguides, modulators, detectors, laser attach). [Co-packaged optics (CPO)](https://www.insidedeeptech.com/co-packaged-optics-cpo-full-guide/) usually means optical engines absorbed onto switch packages. [Linear pluggable optics (LPO)](https://www.insidedeeptech.com/linear-pluggable-optics-lpo-full-guide/) keeps the front-panel cage and strips module DSP. Optical I/O is the XPU-side (and sometimes memory-side) chiplet path that tries to give scale-up the reach of fiber at energy closer to in-package copper. Inside Deep Tech's interconnect map in [NVLink, InfiniBand, and UALink](https://www.insidedeeptech.com/nvlink-infiniband-ualink-ai-gpu-interconnect-full-guide/) separates scale-up from scale-out. Optical I/O is how vendors propose to stretch the scale-up column across packages and racks once copper runs out of meters and watts. ## Why copper scale-up hits a wall Electrical I/O still delivers outstanding bandwidth density and latency inside a package and across short board or cable reaches. Intel's OCI briefing puts practical copper reach on the order of about one meter or less for the high-bandwidth, low-power regime AI pods want. Ayar Labs' August 2025 validation write-up makes the same cluster geometry explicit: roughly a meter of cable for a rack's worth of GPUs at 200G-class rates, about 15 meters for multi-rack, and on the order of 100 meters for a full cluster. Pluggable optics already solve reach for Ethernet and InfiniBand scale-out, but at power and cost that hurt when every XPU port wants many terabits. Intel cites roughly **15 pJ/bit** for typical pluggable modules versus about **5 pJ/bit** for its OCI chiplet demonstration. That gap is the procurement argument for Optical I/O: keep the energy of a co-packaged path while gaining fiber reach. Scale-up fabrics such as [UALink](https://www.insidedeeptech.com/ualink-ultra-accelerator-link-ai-full-guide/) and proprietary NVLink still assume dense electrical domains first. Optical I/O is complementary plumbing for when those domains must span beyond copper without falling back to a full pluggable tax on every link. ## Architecture: UCIe attach, DWDM ports, and lasers Most Optical I/O designs share a sandwich: - A short-reach electrical die-to-die interface (UCIe Standard package rates are the open path Ayar Labs emphasizes; proprietary D2D still appears in closed stacks). - Retimer or protocol adapter logic so host UCIe (or other) traffic can ride an optical serdes without rewriting the XPU die. - A silicon photonics integrated circuit with modulators, detectors, and wavelength multiplexing (microrings are common in TeraPHY-class demos). - A laser strategy: off-chip multi-wavelength sources (Ayar SuperNova) or on-chip laser/SOA integration (Intel OCI). - Fiber attach (often SMF, sometimes with polarization management on the receive path) and thermal control loops that track ring resonances as XPUs heat and cool. For the chiplet electrical side, see Inside Deep Tech's [Chiplets and UCIe Full Guide](https://www.insidedeeptech.com/chiplets-ucie-full-guide/). UCIe is not optional marketing. It is how a third-party optical engine claims it can land next to someone else's GPU, CPU, or switch die without a one-off interposer protocol. | Layer | Job | Optical I/O example | | --------------------- | ------------------------------ | ---------------------------------------- | | Die-to-die electrical | Short package hop to/from XPU | UCIe Standard @ 16 Gbps/lane (Ayar) | | Retimer / adapter | Map host protocol onto optics | UCIe optical retimer (TeraPHY) | | Photonic I/O | DWDM TX/RX over SMF | 16λ microrings @ 32 Gbps NRZ | | Light source | Multi-wavelength power | SuperNova off-chip or on-chip lasers | | System role | Stretch scale-up beyond copper | XPU-to-XPU, XPU-to-switch, memory fabric | ## Ayar Labs TeraPHY: UCIe optical retimer at 8 Tbps On **March 31, 2025**, Ayar Labs announced what it called the industry's first [UCIe optical interconnect chiplet](https://www.businesswire.com/news/home/20250331044779/en/Ayar-Labs-Unveils-Worlds-First-UCIe-Optical-Chiplet-for-AI-Scale-Up-Architectures?ref=insidedeeptech.com) for AI scale-up, built around the **TeraPHY** optical I/O engine and powered by the company's **SuperNova** 16-wavelength light source. Public materials put bidirectional bandwidth at **8 Tbps**. Hot Chips 2025 materials from Ayar Labs describe the third-generation device in engineering terms: a fully retimed UCIe optical chiplet, first demonstration of 16-wavelength microring links, DWDM over SMF, and up to **8.192 Tbps** bidirectional bandwidth. The UCIe side is framed as Standard package signaling at 16 Gbps per lane with termination, 512 Gbps bidirectional per UCIe module, and 16 modules per chip. Each optical port is described as 16 TX and 16 RX lanes at 32 Gbps NRZ (about 1.024 Tbps bidirectional per port) across eight optical ports. In an **August 28, 2025** engineering validation post, Ayar Labs reported EVT-class results that matter more to buyers than slideware: error-free UCIe link testing across modules, optical links with multi-dB margin, thermal cycling in a 30 to 80 C liquid-cooled XPU-like profile with BER under a 1e-12 class target, and emulated thermal tracking up to about **800 C/s**. An end-to-end UCIe-over-optics duplex test ran error-free for more than 10 hours with end-to-end latency under **25 ns** between data generators. The company framed the work as completing EVT and moving through DVT toward high-volume manufacturing, not as a shelf SKU with a public GPU BOM date. Process context from secondary technical reporting places TeraPHY builds on GlobalFoundries 45SPCLO silicon photonics, with a migration path discussed toward TSMC electrical nodes plus TSMC photonics and packaging flows, and integration help from ASIC houses such as Alchip. Treat foundry and OSAT choices as roadmap claims until a named shipping module is on a hyperscaler AVL. ## Intel OCI: 4 Tbps integrated Optical Compute Interconnect At **OFC 2024**, Intel's Integrated Photonics Solutions group demonstrated a fully integrated **Optical Compute Interconnect (OCI)** chiplet co-packaged with an Intel CPU and running live data. Intel's [June 26, 2024 newsroom brief](https://newsroom.intel.com/artificial-intelligence/intel-unveils-first-integrated-optical-io-chiplet?ref=insidedeeptech.com) is the primary citation. The first OCI implementation supports up to **4 Tbps bidirectional** transfer, described as compatible with **PCIe Gen5**. The channelization is **64 channels of 32 Gbps** in each direction over up to **100 meters** of fiber (with a practical note that time-of-flight may push real deployments toward tens of meters). The demo used eight fiber pairs, each carrying eight DWDM wavelengths at 200 GHz spacing. Intel's differentiator pitch is on-chip laser and SOA integration inside the PIC, stacked with an advanced-node electrical IC, so the chiplet does not require an external laser module of the SuperNova style. Energy is cited at about **5 pJ/bit** versus about **15 pJ/bit** for pluggable modules. Intel also cites its high-volume silicon photonics track record of more than **8 million PICs** and more than **32 million on-chip lasers** shipped in pluggable form factors, with a laser FIT rate described as less than 0.1. Honest status from the same brief: the OCI chiplet is a **prototype**. Intel says it is working with select customers to co-package OCI with their SoCs. That is not the same as a 2026 GPU SKU with Optical I/O ports on the AVL. [Silicon Photonics: A Full Guide to the Optical Chips Moving AI DataDevice, foundry, and packaging context for the PICs that Optical I/O engines build on.![](https://www.insidedeeptech.com/favicon.ico)Inside Deep Tech](https://www.insidedeeptech.com/silicon-photonics-ai-data-centers-full-guide/) ## Marvell, Celestial AI, and Photonic Fabric On **February 2, 2026**, [Marvell announced it completed its acquisition of Celestial AI](https://www.marvell.com/company/newsroom/marvell-completes-acquisition-of-celestial-ai.html?ref=insidedeeptech.com). Celestial's **Photonic Fabric** platform moves into Marvell's Data Center Group as an optical interconnect technology aimed at high-bandwidth, low-latency scale-up across large AI deployments. Marvell's own forward-looking financial framing (not a shipping schedule for every hyperscaler) expects initial revenue contributions from Celestial in the **second half of fiscal 2028**, ramping to a **$500 million annualized run rate** by the fourth quarter of fiscal 2028 and **$1 billion** by the fourth quarter of fiscal 2029\. Those numbers are company projections. They are useful as a capitalization signal, not as proof that Photonic Fabric ports are on 2026 training clusters. Marvell's Photonic Fabric technology blog describes a shared-memory oriented stack: a Photonic Fabric Memory Module supporting up to **8x DDR5 DIMMs** with a **72 GB HBM** cache and **7.2 Tbps** of optical fabric bandwidth, plus a PF-NIC path framed around **CXL 3.1** and **PCIe Gen6** optical networking for memory disaggregation across racks on the order of tens of meters, with near-NUMA access cited around **under 350 nanoseconds**. That is a different buyer story than Ayar's UCIe retimer: memory pooling and inference KV-cache scaling, not only GPU-to-GPU scale-up. Acquisition decks circulating around the deal also quoted Photonic Fabric chiplet bandwidths in the **16 Tbps** class, roughly **2.5 pJ/bit** full E-O-E link energy, and on the order of **50 meter** reach for gen2-style links. Prefer Marvell primary pages when you put those figures in a purchase memo, and treat deck metrics as vendor claims until a public datasheet lands. | Vendor path | Attach model | Headline bandwidth (vendor) | 2026 status (primary) | | ----------------------- | ------------------------------ | --------------------------- | ------------------------------------ | | Ayar Labs TeraPHY | UCIe optical retimer chiplet | 8 Tbps bidirectional | EVT done; DVT toward HVM (Aug 2025) | | Intel OCI | Integrated PIC+EIC chiplet | 4 Tbps bidirectional | OFC 2024 prototype; select customers | | Marvell Photonic Fabric | Celestial platform in DC Group | 7.2 Tbps PFMM fabric (blog) | Acquisition closed Feb 2, 2026 | ## Optical I/O vs CPO vs LPO vs electrical scale-up Mixing labels is how RFQs get expensive. Keep the columns separate. | Technology | Where it lives | Primary buyer job | Not a substitute for | | ------------------- | --------------------------- | ------------------------------------- | ----------------------------- | | Optical I/O | XPU / memory package edge | Fiber-reach scale-up / disaggregation | Switch CPO or front-panel LPO | | CPO | Switch (or similar) package | Kill pluggable power on spines | XPU package Optical I/O | | LPO | Pluggable cage, DSP-less | Lower module watts on short SMF | Chiplet Optical I/O | | UALink / NVLink | Electrical scale-up domain | Dense low-latency XPU pods | 100 m cluster fiber | | Ultra Ethernet / IB | Scale-out backend | Node-to-node training/inference | In-package D2D | Optical Circuit Switching is another neighbor, not a synonym. [OCS](https://www.insidedeeptech.com/optical-circuit-switching-ocs-ai-data-centers-full-guide/) rewires photonic paths in the fabric. Optical I/O is how a package speaks light in the first place. [Co-Packaged Optics: A Full Guide to CPO, LPO, and Why AI Switches Absorb the TransceiverSwitch-side photonics that buyers often confuse with XPU-side Optical I/O.![](https://www.insidedeeptech.com/favicon.ico)Inside Deep Tech](https://www.insidedeeptech.com/co-packaged-optics-cpo-full-guide/) ## Honest limits: when copper and pluggables still win ⚖️ Inside Deep Tech's take: Optical I/O is the most important packaging bet for multi-rack scale-up after copper, but it is still a 2026 qualification story more than a 2026 default BOM line. Buy the primary demos (TeraPHY EVT, OCI OFC, Photonic Fabric acquisition) as evidence the industry is serious. Do not schedule training clusters on unshipped chiplet optics when UALink/NVLink copper domains and mature pluggables already clear the job. Named downsides to put on the whiteboard: - Volume shipping gap: public materials still emphasize EVT/DVT, prototypes, and select co-package programs rather than broad GPU AVL listings as of September 2026. - Laser and fiber attach yield: off-chip sources, on-chip lasers, FAUs, and polarization management remain hard manufacturing problems. - Thermal tracking: microring links need control loops that survive XPU power transients; demos are promising, fleet evidence is thinner. - Software and operations: Optical I/O does not replace collective libraries, fabric managers, or the need to separate scale-up from scale-out on the rack drawing. - Category confusion: buying CPO switches or LPO modules does not automatically give you XPU Optical I/O, and the reverse is also true. When copper still wins: single-rack dense pods, mature NVLink or early UALink electrical domains, teams that cannot absorb packaging risk on the critical path, and any link that is short enough that a retimed copper cable or board trace beats fiber attach complexity. When pluggables still win: standardized Ethernet/IB scale-out, field-replaceable optics, and halls that already standardized on OSFP/QSFP supply chains. Optical I/O is trying to steal the high-radix, low-pJ scale-up cases those modules were never optimized for. ## What operators should do Monday - On every rack drawing, label links as electrical scale-up, Optical I/O scale-up, CPO switch, or pluggable scale-out. Refuse vendor slides that collapse those four into one word. - Ask Optical I/O vendors for UCIe revision, bidirectional Tbps per chiplet, laser model (on-chip vs external), fiber reach, pJ/bit measurement method, and dated EVT/DVT/HVM status. - If you are buying UALink or NVLink pods in 2026, treat Optical I/O as a 2027-plus option for multi-rack stretch, not as a mandatory cross-out of copper. - If you care about memory disaggregation, read Marvell Photonic Fabric and CXL materials separately from Ayar UCIe retimer claims. They solve overlapping but different RFQs. - Cite primary sources: Intel OCI newsroom (June 2024), Ayar BusinessWire (March 2025) plus August 2025 validation post, Marvell Celestial close (February 2026). The industry is not inventing Optical I/O because copper stopped working inside a package. It is inventing Optical I/O because the AI pod is trying to become a multi-rack machine without paying pluggable energy on every XPU shoreline. The teams that win will demand BER, thermal, and AVL evidence, not another synonym for "photonics." [Read the Silicon Photonics Full Guide](https://www.insidedeeptech.com/silicon-photonics-ai-data-centers-full-guide/) --- ## FAQ #### What is Optical I/O in AI data centers? Optical I/O is co-packaged or near-package photonic connectivity that moves multi-terabit traffic on and off XPUs, switches, or memory appliances over fiber. In modern designs a photonic chiplet often attaches over UCIe, retimes host traffic, and launches DWDM wavelengths onto single-mode fiber so scale-up can exceed copper reach. #### How is Optical I/O different from silicon photonics? Silicon photonics is the device and manufacturing platform (waveguides, modulators, detectors, lasers on silicon). Optical I/O is a system product category that uses silicon photonics (and packaging) to put usable terabit links on compute packages. One is the toolkit; the other is the XPU-edge interconnect job. #### How is Optical I/O different from CPO or LPO? CPO typically co-packages optical engines with switch ASICs to cut front-panel pluggable power. LPO keeps pluggable form factors but removes module DSP for short reaches. Optical I/O focuses on chiplet engines at the XPU or memory package for scale-up and disaggregation. They can coexist in one hall. #### What did Ayar Labs announce for TeraPHY? In March 2025 Ayar Labs announced a UCIe optical interconnect chiplet built on TeraPHY with an 8 Tbps bandwidth claim and a SuperNova 16-wavelength light source. Hot Chips 2025 materials detail an 8.192 Tbps bidirectional retimer architecture. August 2025 posts describe EVT validation including thermal tracking and UCIe-over-optics link tests. #### What is Intel OCI? Optical Compute Interconnect is Intel's integrated photonic chiplet demonstrated at OFC 2024\. The first implementation supports 4 Tbps bidirectional bandwidth, 64 channels at 32 Gbps each direction, up to about 100 meters of fiber, and roughly 5 pJ/bit. Intel describes it as a prototype for select customer co-package work. #### What happened to Celestial AI? Marvell completed its acquisition of Celestial AI on February 2, 2026, and placed Photonic Fabric technology inside Marvell's Data Center Group. Marvell's forward-looking statements point to Celestial-related revenue starting in the second half of fiscal 2028 with large annualized run-rate targets thereafter. #### Should buyers replace copper scale-up with Optical I/O in 2026? Only for programs that truly need multi-rack fiber-reach scale-up and can absorb packaging qualification risk. Dense single-rack NVLink or emerging UALink electrical domains still clear most 2026 training schedules. Treat Optical I/O as a parallel qualification track, not a drop-in cable swap. --- [Explore more Inside Deep Tech AI infrastructure guides](https://www.insidedeeptech.com/)