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# NVIDIA Feynman: A Full Guide to the 2028 GPU, Rosa CPU, Kyber NVL1152, Custom HBM and Limits
- URL: https://www.insidedeeptech.com/nvidia-feynman-rosa-kyber-nvl1152-full-guide/
- Published: 2026-10-27T07:09:08.000Z
- Updated: 2026-10-27T07:09:07.000Z
- Description: NVIDIA Feynman full guide: where the 2028 GPU sits after Rubin Ultra, what NVIDIA has confirmed (die stacking, custom HBM, Rosa CPU, LP40, Kyber NVL1152, NVLink 8 CPO), what is only reported (TSMC A16), the supply chain and the honest limits.
- Author: Austin Heaton
- Tags: AI, Hardware, Deep Tech

At GTC 2026 in March, Jensen Huang put one word at the far right of NVIDIA's roadmap and said it plainly: ["The next generation from here is Feynman."](https://www.tomshardware.com/pc-components/gpus/nvidia-updates-data-center-roadmap-with-rosa-cpu-and-stacked-feynman-gpus-optical-nvlink-groq-lpus-with-nvfp4-and-nvlink-also-on-deck?ref=insidedeeptech.com) The slide gave it a year, 2028, and a short list of ideas: [die stacking, custom HBM, a new Rosa CPU and NVLink 8 over co-packaged optics](https://s201.q4cdn.com/141608511/files/doc%5Fevents/2026/Mar/16/GTC-2026-Keynote.pdf?ref=insidedeeptech.com).

That's less than most coverage implies. NVIDIA Feynman has no published FLOPS, memory capacity, power figure or confirmed process node. It does have a fixed roadmap slot, named building blocks and a supply chain already being built for it.

This full guide covers where NVIDIA Feynman sits after Rubin and [Rubin Ultra](https://www.insidedeeptech.com/nvidia-rubin-ultra-kyber-nvl576-full-guide/), what NVIDIA has confirmed, what has only been reported, the TSMC, HBM and packaging supply chain behind it, and the honest limits, all as of October 27, 2026.

Last updated: October 27, 2026.

## Key Takeaways

- **NVIDIA Feynman** is the [2028 architecture on NVIDIA's official roadmap](https://s201.q4cdn.com/141608511/files/doc%5Fevents/2026/Mar/16/GTC-2026-Keynote.pdf?ref=insidedeeptech.com), following Rubin in 2026 and Rubin Ultra in 2027.
- NVIDIA has confirmed [stacked GPU dies, custom HBM, the Rosa CPU, the LP40 LPU, BlueField-5 and ConnectX-10](https://blogs.nvidia.com/blog/gtc-2026-news/?ref=insidedeeptech.com) as parts of the Feynman generation.
- Feynman is the first NVIDIA generation to scale up over both copper and co-packaged optics, through [Kyber NVL144 and an all-to-all Kyber NVL1152](https://developer.nvidia.com/blog/nvidia-vera-rubin-pod-seven-chips-five-rack-scale-systems-one-ai-supercomputer/?ref=insidedeeptech.com).
- Reports say Feynman will be built on [TSMC's A16 process with backside power](https://www.techpowerup.com/351607/nvidia-secures-tsmc-a16-node-for-next-generation-feynman-gpus?ref=insidedeeptech.com), but NVIDIA hasn't confirmed any node.
- Honest limit: NVIDIA hasn't published a single Feynman performance, memory or power figure, and [its August 2026 earnings call never mentioned Feynman by name](https://s201.q4cdn.com/141608511/files/content%5Ffiles/TRANSCRIPT%5F-NVIDIA-Corp-NVDA-US-Q2-2027-Earnings-Call-26-August-2026-5%5F00-PM-ET.pdf?ref=insidedeeptech.com).

💡

Inside Deep Tech's take: Feynman is less a chip announcement than a statement of direction. NVIDIA is telling the industry that after 2027 the gains come from stacking silicon vertically, moving memory control into HBM and replacing copper with light. Each of those is a manufacturing bet, not just a design choice.

## What is NVIDIA Feynman?

NVIDIA Feynman is NVIDIA's data center GPU architecture after Rubin, named for the physicist Richard Feynman in the line of Hopper, Blackwell and Rubin.

Like Vera Rubin, Feynman isn't just a GPU. NVIDIA describes it as a platform: a new GPU, a new CPU, a new inference processor, new networking chips and new racks, all designed together. NVIDIA's own GTC 2026 summary lists [Rosa, LP40, BlueField-5 and CX10 alongside the Feynman GPU](https://blogs.nvidia.com/blog/gtc-2026-news/?ref=insidedeeptech.com), connected through Kyber racks.

DCD reported NVIDIA's rhythm as [a new GPU or LPU every year and a new CPU every two years](https://www.datacenterdynamics.com/en/news/nvidia-updates-data-center-product-roadmap-following-lpu-launch-at-gtc-2026/?ref=insidedeeptech.com). Feynman is the 2028 reset, when almost every chip in the system changes at once.

The baseline for every Feynman comparison is the rack NVIDIA ships today, covered in Inside Deep Tech's [Vera Rubin NVL72 full guide](https://www.insidedeeptech.com/nvidia-vera-rubin-nvl72-full-guide/).

## Where Feynman sits on the NVIDIA roadmap

Feynman first appeared at GTC 2025\. That keynote's roadmap slide put it in the 2028 column with ["Next-Gen HBM", a Vera CPU, an 8th-generation NVSwitch labeled "NVL-Next", Spectrum7 at 204T with CPO and ConnectX-10](https://s201.q4cdn.com/141608511/files/doc%5Fdownloads/2025/03/GTC2025%5FKeynote.pdf?ref=insidedeeptech.com). There were no numbers attached.

A year later the picture sharpened. The GTC 2026 roadmap swapped "Next-Gen HBM" for ["Die Stacking" and "Custom HBM", replaced Vera with a new Rosa CPU and named the scale-up fabric "NVLink 8 CPO"](https://s201.q4cdn.com/141608511/files/doc%5Fevents/2026/Mar/16/GTC-2026-Keynote.pdf?ref=insidedeeptech.com). ComputerBase noted that [Rosa replaced the Vera placeholder from the 2025 slide](https://www.computerbase.de/news/grafikkarten/nvidia-roadmap-feynman-nutzt-gpu-die-stacking-custom-hbm-und-rosa-cpu.96567/?ref=insidedeeptech.com).

The table below lines up the four generations using only what NVIDIA has put on its own slides and product pages, plus clearly labeled reports where NVIDIA is silent.

| Item         | Blackwell                | Rubin                         | Rubin Ultra                                       | Feynman                                |
| ------------ | ------------------------ | ----------------------------- | ------------------------------------------------- | -------------------------------------- |
| Roadmap year | 2024 to 2025             | 2026                          | 2027                                              | 2028                                   |
| GPU package  | Two reticle-limited dies | Two reticle-limited dies      | Four dies in 2025 plan; two-die redesign reported | Stacked GPU dies                       |
| Transistors  | 208 billion              | 336 billion                   | Not disclosed                                     | Not disclosed                          |
| Process node | Custom TSMC 4NP          | Not named by NVIDIA           | Not named by NVIDIA                               | Not disclosed; TSMC A16 reported       |
| HBM          | 8 stacks HBM3e           | 8 stacks HBM4, 288 GB         | 16 stacks HBM4e, 1 TB                             | Custom HBM                             |
| Host CPU     | Grace                    | Vera                          | Vera                                              | Rosa                                   |
| Scale-up     | NVLink 5, 1800 GB/s      | NVLink 6, 3600 GB/s           | NVLink 7, 3600 GB/s                               | NVLink 8 CPO                           |
| Scale-out    | Spectrum5 51T, CX8 800G  | Spectrum6 102T CPO, CX9 1600G | Spectrum6, CX9                                    | Spectrum7 204T CPO, CX10               |
| Racks        | Oberon NVL72             | Oberon NVL72                  | Kyber NVL144, Oberon NVL72                        | Kyber NVL144 and NVL1152, Oberon NVL72 |
| LPU / DPU    | None / BlueField-3       | LP30 / BlueField-4            | LP35 / BlueField-4                                | LP40 / BlueField-5                     |

Source: [NVIDIA GTC 2025 keynote](https://s201.q4cdn.com/141608511/files/doc%5Fdownloads/2025/03/GTC2025%5FKeynote.pdf?ref=insidedeeptech.com) and [GTC 2026 keynote](https://s201.q4cdn.com/141608511/files/doc%5Fevents/2026/Mar/16/GTC-2026-Keynote.pdf?ref=insidedeeptech.com) roadmap slides; [Blackwell architecture page](https://www.nvidia.com/en-us/data-center/technologies/blackwell-architecture/?ref=insidedeeptech.com); [Rubin GPU architecture blog](https://developer.nvidia.com/blog/inside-nvidia-rubin-gpu-architecture-powering-the-era-of-agentic-ai/?ref=insidedeeptech.com); [Vera Rubin NVL72 product page](https://www.nvidia.com/en-us/data-center/vera-rubin-nvl72/?ref=insidedeeptech.com); Rubin Ultra redesign as [reported by Tom's Hardware](https://www.tomshardware.com/tech-industry/artificial-intelligence/nvidia-reportedly-cancels-quad-die-rubin-ultra-gpu-in-favor-of-dual-gpu-design-report-claims-complex-design-purportedly-scrapped-over-manufacturing-execution-concerns?ref=insidedeeptech.com); A16 as [reported by TechPowerUp citing DigiTimes](https://www.techpowerup.com/351607/nvidia-secures-tsmc-a16-node-for-next-generation-feynman-gpus?ref=insidedeeptech.com).

Two things stand out. The Feynman column is mostly words, not numbers. And NVLink bandwidth stays flat at [3,600 GB/s](https://s201.q4cdn.com/141608511/files/doc%5Fevents/2026/Mar/16/GTC-2026-Keynote.pdf?ref=insidedeeptech.com) from Rubin to Rubin Ultra, then changes medium rather than speed. The next jump is about reach, not per-link bandwidth.

## What NVIDIA has actually confirmed

Strip away the analyst notes and the confirmed list is short. Every item here comes from NVIDIA or its CEO on stage.

- **A new GPU with die stacking.** Huang confirmed stacked GPU dies during the GTC 2026 keynote, [heise reported](https://www.heise.de/en/news/Nvidia-Feynman-comes-with-stacked-GPU-dies-and-custom-HBM-11214678.html?ref=insidedeeptech.com), and the roadmap slide shows a visibly smaller GPU package than Rubin.
- **Custom HBM.** The [GTC 2026 slide](https://s201.q4cdn.com/141608511/files/doc%5Fevents/2026/Mar/16/GTC-2026-Keynote.pdf?ref=insidedeeptech.com) lists custom HBM for Feynman. NVIDIA hasn't said which HBM generation or how many stacks.
- **Rosa CPU.** A new CPU named for Rosalind Franklin, listed in [NVIDIA's GTC 2026 summary](https://blogs.nvidia.com/blog/gtc-2026-news/?ref=insidedeeptech.com), built on a new Arm core called Rigel.
- **LP40.** The next LPU, the low-latency inference line Huang described as [uniting NVIDIA's scale with Groq](https://www.tomshardware.com/pc-components/gpus/nvidia-updates-data-center-roadmap-with-rosa-cpu-and-stacked-feynman-gpus-optical-nvlink-groq-lpus-with-nvfp4-and-nvlink-also-on-deck?ref=insidedeeptech.com), now on NVLink per the [roadmap slide](https://s201.q4cdn.com/141608511/files/doc%5Fevents/2026/Mar/16/GTC-2026-Keynote.pdf?ref=insidedeeptech.com).
- **BlueField-5 and ConnectX-10.** New DPU and SuperNIC generations, both [named by NVIDIA](https://blogs.nvidia.com/blog/gtc-2026-news/?ref=insidedeeptech.com) for the Feynman platform.
- **Kyber copper and Kyber CPO scale-up.** Huang said Feynman marks [the first time NVIDIA scales up with both copper and co-packaged optics](https://www.tomshardware.com/pc-components/gpus/nvidia-updates-data-center-roadmap-with-rosa-cpu-and-stacked-feynman-gpus-optical-nvlink-groq-lpus-with-nvfp4-and-nvlink-also-on-deck?ref=insidedeeptech.com), per Tom's Hardware.

Everything else, including node, power, memory capacity and performance, is a report or an estimate.

## Die stacking: why Feynman goes vertical

Every NVIDIA flagship since Blackwell has used a 2.5D layout. Two large GPU dies sit side by side on a silicon interposer, with HBM stacks around them. Blackwell joins its dies with a [10 TB/s chip-to-chip link](https://www.nvidia.com/en-us/data-center/technologies/blackwell-architecture/?ref=insidedeeptech.com). Rubin does the same with NV-HBI across [336 billion transistors](https://developer.nvidia.com/blog/inside-nvidia-rubin-gpu-architecture-powering-the-era-of-agentic-ai/?ref=insidedeeptech.com).

The problem is the reticle. A single exposure on an EUV scanner can only print a die up to a fixed size, so NVIDIA has been scaling by adding dies sideways. Inside Deep Tech's [EUV lithography full guide](https://www.insidedeeptech.com/euv-lithography-asml-machines-full-guide/) explains why that ceiling exists and why High-NA EUV makes it smaller, not bigger.

Stacking dies is the way out. It shortens wires between logic blocks and lets the package grow upward. heise described the Feynman sketch on NVIDIA's slide as [significantly smaller than Rubin and Rubin Ultra](https://www.heise.de/en/news/Nvidia-Feynman-comes-with-stacked-GPU-dies-and-custom-HBM-11214678.html?ref=insidedeeptech.com) for exactly this reason.

The catch is heat. heise points out that chipmakers [haven't solved heat dissipation from the lower dies for mass production](https://www.heise.de/en/news/Nvidia-Feynman-comes-with-stacked-GPU-dies-and-custom-HBM-11214678.html?ref=insidedeeptech.com), and that so far 3D stacking has mainly been used for cache chiplets. It also estimates Feynman could exceed 2,000 watts. That's heise's estimate, not an NVIDIA figure.

NVIDIA hasn't said how the stack is arranged. It could be logic on logic, logic on SRAM, or compute dies on an active base die. ComputerBase reported that [NVIDIA gave no detail on how the stacking works](https://www.computerbase.de/news/grafikkarten/nvidia-roadmap-feynman-nutzt-gpu-die-stacking-custom-hbm-und-rosa-cpu.96567/?ref=insidedeeptech.com).

## Custom HBM and NVHBM: moving the memory controller

In standard HBM the memory controller lives on the GPU. Custom HBM moves logic into the stack's base die, built on a logic process. heise explains that with custom HBM, customers like NVIDIA can [design their own control logic for the memory stack](https://www.heise.de/en/news/Nvidia-Feynman-comes-with-stacked-GPU-dies-and-custom-HBM-11214678.html?ref=insidedeeptech.com).

In August 2026 NVIDIA gave that idea a name. NVHBM puts NVIDIA's custom memory controller into the HBM base die, and NVIDIA says it delivers [up to 30% more memory bandwidth, 15% lower HBM power and up to 25% more XPU compute die area than standard HBM4E](https://blogs.nvidia.com/blog/nvlink-fusion-nvhbm-custom-high-bandwidth-memory/?ref=insidedeeptech.com).

Note the wording. NVIDIA says NVHBM is ["built on the same technology that NVIDIA will use for future GPUs"](https://blogs.nvidia.com/blog/nvlink-fusion-nvhbm-custom-high-bandwidth-memory/?ref=insidedeeptech.com). It's offered first to NVLink Fusion partners, with Amazon's Annapurna Labs the first collaborator. NVIDIA didn't say "Feynman" in that announcement, though the roadmap's custom HBM line and the timing point the same way.

TrendForce, citing Seoul Economic Daily, reported that NVIDIA asked Samsung, SK hynix and Micron to [build NVHBM base dies on TSMC's 3nm process](https://www.trendforce.com/news/2026/10/19/news-nvidia-reportedly-pushes-tsmc-3nm-nvhbm-base-dies-for-samsung-sk-hynix-micron-in-unlikely-foundry-tie-up/?ref=insidedeeptech.com), with industry estimates putting TSMC 3nm yields above 90% against about 60% for Samsung's 2nm. None of the companies has confirmed the arrangement.

🧠

Inside Deep Tech's take: custom HBM is the most underrated part of Feynman. If the memory controller moves into the stack, the HBM base die becomes a TSMC logic wafer, and the three memory makers become partly dependent on their biggest customer's foundry. That shifts bargaining power toward NVIDIA and TSMC.

## The Rosa CPU and the Rigel core

Rosa replaces Vera as the host CPU, keeping NVIDIA's two-year CPU rhythm. In July 2026 NVIDIA said Rosa will use [Rigel, a next-generation Arm v9.2 core with higher per-core performance than Vera's Olympus core in the same silicon footprint](https://blogs.nvidia.com/blog/nvidia-vera-max-single-threaded-cpu-at-scale/?ref=insidedeeptech.com), with better instruction delivery, a larger L2 cache and more efficient memory handling.

Compiler work confirms Rigel is real silicon in progress. Phoronix reported that [initial Rigel support was merged into LLVM Clang](https://www.phoronix.com/news/LLVM-Clang-NVIDIA-Rosa-Rigel?ref=insidedeeptech.com) for the next-generation Rosa CPU. NVIDIA hasn't published a Rosa core count, clock speed or memory configuration.

## Kyber NVL1152, NVLink 8 and co-packaged optics

Kyber is the vertical-blade rack that follows Oberon. NVIDIA's March 2026 technical blog says Kyber [doubles the NVLink domain per rack to 144 GPUs and scales to an all-to-all NVL1152 with direct optical rack-to-rack links](https://developer.nvidia.com/blog/nvidia-vera-rubin-pod-seven-chips-five-rack-scale-systems-one-ai-supercomputer/?ref=insidedeeptech.com). It adds that Kyber "provides the foundation for the next era of extreme scale-up AI computing using NVIDIA Feynman."

NVL1152 means 1,152 GPU packages in one NVLink domain, [16x the count of an NVL72 rack](https://developer.nvidia.com/blog/nvidia-vera-rubin-pod-seven-chips-five-rack-scale-systems-one-ai-supercomputer/?ref=insidedeeptech.com). For comparison, a whole Vera Rubin POD today is [1,152 Rubin GPUs across 40 racks](https://developer.nvidia.com/blog/nvidia-vera-rubin-pod-seven-chips-five-rack-scale-systems-one-ai-supercomputer/?ref=insidedeeptech.com), but split into separate 72-GPU NVLink domains. Feynman's pitch is to make that whole room behave like one machine.

Copper can't do that, which is why every NVLink domain so far stops at the rack edge. NVLink 8 CPO puts optical engines beside the switch silicon so the fabric can leave the rack. ComputerBase reported that [optical scale-up is reserved for Kyber, while Feynman keeps an Oberon NVL72 option](https://www.computerbase.de/news/grafikkarten/nvidia-roadmap-feynman-nutzt-gpu-die-stacking-custom-hbm-und-rosa-cpu.96567/?ref=insidedeeptech.com) for buyers who don't want optics.

NVIDIA already ships CPO, but only in switches. Its Quantum-X and Spectrum-X photonics switches were introduced with [3.5x better power efficiency and 63x greater signal integrity](https://blogs.nvidia.com/blog/nvidia-keynote-at-gtc-2025-ai-news-live-updates/?ref=insidedeeptech.com) than pluggable optics. Feynman extends CPO from scale-out switches to the scale-up fabric itself, which is a much harder reliability problem. Inside Deep Tech's [co-packaged optics full guide](https://www.insidedeeptech.com/co-packaged-optics-cpo-full-guide/) covers what has actually shipped and what is still a roadmap slide.

## Process node: the TSMC A16 reports

NVIDIA hasn't said what node Feynman uses. It didn't name a node for Rubin in its architecture blog either. What exists is a chain of reports.

- TrendForce reported in February 2026 that [NVIDIA may be the first customer for TSMC's 1.6nm-class A16 in 2028](https://www.trendforce.com/news/2026/02/02/news-tsmc-2nm-reportedly-tight-amid-mobile-hpc-demand-nvidia-may-be-first-to-adopt-1-6nm-in-2028/?ref=insidedeeptech.com).
- TechPowerUp, citing DigiTimes in August 2026, reported that NVIDIA [secured A16 for Feynman, skipping N2](https://www.techpowerup.com/351607/nvidia-secures-tsmc-a16-node-for-next-generation-feynman-gpus?ref=insidedeeptech.com), with SoIC 3D stacking and CoWoS-class packaging.
- TSMC itself moved A16 volume production [from late 2026 to 2027](https://www.tomshardware.com/tech-industry/semiconductors/tsmc-unveils-process-technology-roadmap-through-2029-a12-a13-n2u-announced-a16-slips-to-2027?ref=insidedeeptech.com) at its April 2026 symposium.

A16 is TSMC's N2-family node with Super Power Rail, a backside power delivery scheme that feeds power from beneath the transistors. That's attractive for a chip drawing well over a kilowatt, because it frees the front side for signal wiring. Inside Deep Tech's [TSMC 2nm full guide](https://www.insidedeeptech.com/tsmc-2nm-n2-a16-nanosheet-full-guide/) covers A16, Super Power Rail and the 2027 slip in detail.

Inside Deep Tech's take: A16 for Feynman is plausible and consistent across sources, but it's still a supply chain report. A 2027 volume start leaves roughly a year of node maturity before a 2028 flagship, which is tight for a reticle-scale, stacked AI die.

## The Feynman supply chain: TSMC, HBM and packaging

Feynman stacks three bottlenecks: leading-edge logic, custom HBM and advanced packaging. NVIDIA is already paying to widen all three.

At GTC Berlin on October 21, 2026, NVIDIA announced capacity deals across its supply chain. Huang's summary was blunt: ["Demand is extraordinary. Capacity is the constraint."](https://nvidianews.nvidia.com/news/nvidia-and-supply-chain-partners-expand-capacity-to-accelerate-ai-infrastructure-buildout?ref=insidedeeptech.com)

| Layer               | Partner                                      | Announced expansion                                        | Timing                     |
| ------------------- | -------------------------------------------- | ---------------------------------------------------------- | -------------------------- |
| Substrates          | IBIDEN, Samsung Electro-Mechanics, Unimicron | 2.5x substrate capacity                                    | Over three years           |
| Advanced packaging  | Amkor                                        | More than 300% more interposer wafer capacity              | By end of 2028             |
| Testing             | KYEC and others                              | $1.1 billion capacity advance; total test capacity doubles | 2026 to 2027               |
| CPO optical engines | SPIL                                         | 15x capacity, then another doubling                        | Mid-2027, then end of 2028 |

Source: [NVIDIA Newsroom, October 21, 2026](https://nvidianews.nvidia.com/news/nvidia-and-supply-chain-partners-expand-capacity-to-accelerate-ai-infrastructure-buildout?ref=insidedeeptech.com). The release doesn't name Feynman; it refers to current and next-generation platforms.

Read the dates. Amkor's interposer build and SPIL's second CPO doubling both land by the end of 2028, Feynman's year, and optical engines get the steepest ramp of any layer.

Memory is the other constraint. TrendForce expects [DRAM to stay tight through 2027](https://www.trendforce.com/presscenter/news/20260804-13166.html?ref=insidedeeptech.com), and custom HBM adds a TSMC logic wafer to every stack. On its August 2026 call, NVIDIA said it expects [supply to remain a bottleneck at least through the end of fiscal year 2028](https://s201.q4cdn.com/141608511/files/content%5Ffiles/TRANSCRIPT%5F-NVIDIA-Corp-NVDA-US-Q2-2027-Earnings-Call-26-August-2026-5%5F00-PM-ET.pdf?ref=insidedeeptech.com), which ends in January 2028, just before Feynman's year.

The money explains the urgency. On the same call, NVIDIA put its revenue opportunity at [about $18 billion per gigawatt for Hopper, $25 billion for Grace Blackwell and $40 billion for Vera Rubin](https://s201.q4cdn.com/141608511/files/content%5Ffiles/TRANSCRIPT%5F-NVIDIA-Corp-NVDA-US-Q2-2027-Earnings-Call-26-August-2026-5%5F00-PM-ET.pdf?ref=insidedeeptech.com). NVIDIA gave no Feynman figure.

## Power and cooling: what Feynman racks will need

NVIDIA hasn't published a Feynman TDP or a Kyber rack power figure for 2028\. What it has published is the infrastructure plan. NVIDIA says [800 VDC power distribution will reach full-scale production alongside Kyber](https://developer.nvidia.com/blog/nvidia-800-v-hvdc-architecture-will-power-the-next-generation-of-ai-factories/?ref=insidedeeptech.com), replacing 54 V racks that can't carry megawatt loads efficiently.

Vera Rubin NVL72 racks already run on [45°C warm-water liquid cooling](https://developer.nvidia.com/blog/nvidia-vera-rubin-pod-seven-chips-five-rack-scale-systems-one-ai-supercomputer/?ref=insidedeeptech.com). Stacked dies make cooling harder, because the bottom die pushes heat through the one above. If heise's [2,000-watt estimate](https://www.heise.de/en/news/Nvidia-Feynman-comes-with-stacked-GPU-dies-and-custom-HBM-11214678.html?ref=insidedeeptech.com) is close, Feynman racks will need liquid cooling at the package level, not just the rack level.

## Confirmed, reported and unknown

| Topic              | Status              | What is known                                                           |
| ------------------ | ------------------- | ----------------------------------------------------------------------- |
| Launch year        | Confirmed (roadmap) | 2028 on NVIDIA's GTC 2026 slide                                         |
| Die stacking       | Confirmed           | Stacked GPU dies; layout not disclosed                                  |
| Custom HBM         | Confirmed           | HBM generation, stack count and capacity not disclosed                  |
| NVHBM figures      | NVIDIA claim        | Up to 30% more bandwidth vs standard HBM4E; not tied to Feynman by name |
| Rosa CPU           | Confirmed           | Rigel Arm v9.2 core; core count not disclosed                           |
| Kyber NVL1152      | Confirmed           | All-to-all optical rack-to-rack NVLink domain                           |
| NVLink 8 bandwidth | Unknown             | Only labeled CPO; no GB/s figure                                        |
| Process node       | Reported            | TSMC A16 per DigiTimes and TrendForce                                   |
| Power per GPU      | Estimate            | heise suggests over 2,000 W; no NVIDIA figure                           |
| Performance        | Unknown             | No FLOPS or rack exaflops published                                     |

Source: [GTC 2026 keynote](https://s201.q4cdn.com/141608511/files/doc%5Fevents/2026/Mar/16/GTC-2026-Keynote.pdf?ref=insidedeeptech.com), [NVIDIA NVHBM blog](https://blogs.nvidia.com/blog/nvlink-fusion-nvhbm-custom-high-bandwidth-memory/?ref=insidedeeptech.com), [NVIDIA Rosa and Rigel blog](https://blogs.nvidia.com/blog/nvidia-vera-max-single-threaded-cpu-at-scale/?ref=insidedeeptech.com), [NVIDIA Vera Rubin POD blog](https://developer.nvidia.com/blog/nvidia-vera-rubin-pod-seven-chips-five-rack-scale-systems-one-ai-supercomputer/?ref=insidedeeptech.com), [TechPowerUp](https://www.techpowerup.com/351607/nvidia-secures-tsmc-a16-node-for-next-generation-feynman-gpus?ref=insidedeeptech.com), [heise](https://www.heise.de/en/news/Nvidia-Feynman-comes-with-stacked-GPU-dies-and-custom-HBM-11214678.html?ref=insidedeeptech.com).

## Honest limits: where the Feynman story can break

### 1\. There are no specs yet

Every Feynman versus Rubin performance comparison this year is extrapolation. NVIDIA put hard numbers on Rubin Ultra at GTC 2025, including [15 exaflops of FP4 for NVL576](https://s201.q4cdn.com/141608511/files/doc%5Fdownloads/2025/03/GTC2025%5FKeynote.pdf?ref=insidedeeptech.com). It has put none on Feynman. Treat any Feynman FLOPS figure as an analyst model.

### 2\. Roadmaps move

Rubin Ultra shows how fast a plan changes. It went from a four-die package in a 576-die rack to a [reported two-die redesign](https://www.tomshardware.com/tech-industry/artificial-intelligence/nvidia-reportedly-cancels-quad-die-rubin-ultra-gpu-in-favor-of-dual-gpu-design-report-claims-complex-design-purportedly-scrapped-over-manufacturing-execution-concerns?ref=insidedeeptech.com) and a [reported Kyber slip to 2028](https://www.tomshardware.com/pc-components/gpus/nvidias-kyber-rack-for-rubin-ultra-slips-to-2028?ref=insidedeeptech.com). NVIDIA says its roadmap is intact, but if Kyber slips, Feynman's biggest systems arrive on a rack with very little field time.

### 3\. Stacked logic is unproven at this scale

No one ships a stacked, kilowatt-class AI logic die in volume today. The thermal problem is physics, and stacked yields multiply: one bad die can scrap the stack.

### 4\. Optical scale-up has no track record

Optical links add lasers, fiber attach and new failure modes inside the most latency-sensitive fabric in the data center. NVIDIA hedges with an Oberon NVL72 copper option, which tells you it knows not every buyer will take the optical path in 2028.

### 5\. The node and memory are outside NVIDIA's control

A16 has already slipped once, and custom HBM depends on three memory makers adopting a new base-die flow at the same time. Either can push Feynman volume later even if the design is on time.

🧭

Inside Deep Tech's take: plan for Feynman as a 2028 announcement and a 2029 volume product. That's not a prediction of a delay. It's the pattern every new NVIDIA rack architecture has followed, and Feynman changes more parts at once than any generation before it.

## What NVIDIA Feynman means for you

- **If you buy AI infrastructure:** buy Vera Rubin for 2026 and 2027 capacity. Don't wait for Feynman, because no specs or prices exist, and NVIDIA expects supply to stay tight through fiscal 2028.
- **If you design data centers:** build new halls for 800 VDC and dense liquid cooling, and leave pathways for fiber between racks. Kyber NVL1152 assumes both.
- **If you invest in semiconductors:** watch TSMC A16 volume, custom HBM base-die orders and CPO optical engine capacity. Those are the Feynman signals that show up before NVIDIA publishes a spec.

[NVIDIA Rubin Ultra and Kyber: A Full GuideEverything NVIDIA has confirmed about Rubin Ultra, the Kyber rack, NVL144 and NVL576, 800 VDC power, HBM4E, the reported delays and the honest limits.![](https://www.insidedeeptech.com/favicon.ico)Inside Deep Tech](https://www.insidedeeptech.com/nvidia-rubin-ultra-kyber-nvl576-full-guide/)

[Read the Vera Rubin NVL72 Full Guide](https://www.insidedeeptech.com/nvidia-vera-rubin-nvl72-full-guide/)

---

## FAQ

#### What is NVIDIA Feynman?

NVIDIA Feynman is NVIDIA's data center GPU architecture after Rubin, shown for 2028 on the [GTC 2026 roadmap](https://s201.q4cdn.com/141608511/files/doc%5Fevents/2026/Mar/16/GTC-2026-Keynote.pdf?ref=insidedeeptech.com). It brings stacked GPU dies, custom HBM, the Rosa CPU, the LP40 LPU and NVLink 8 over co-packaged optics.

#### When will NVIDIA Feynman be released?

NVIDIA's roadmap lists Feynman for 2028\. It hasn't given a quarter or a ship date. TechPowerUp reported [mass production in the second half of 2028](https://www.techpowerup.com/351607/nvidia-secures-tsmc-a16-node-for-next-generation-feynman-gpus?ref=insidedeeptech.com), citing DigiTimes.

#### What process node will Feynman use?

NVIDIA hasn't said. Reports from TrendForce and DigiTimes point to [TSMC's A16 node](https://www.trendforce.com/news/2026/02/02/news-tsmc-2nm-reportedly-tight-amid-mobile-hpc-demand-nvidia-may-be-first-to-adopt-1-6nm-in-2028/?ref=insidedeeptech.com) with Super Power Rail backside power.

#### What is the Rosa CPU?

Rosa is the CPU that follows Vera, named for Rosalind Franklin. NVIDIA says it uses the [Rigel Arm v9.2 core](https://blogs.nvidia.com/blog/nvidia-vera-max-single-threaded-cpu-at-scale/?ref=insidedeeptech.com), with higher per-core performance than Vera's Olympus core.

#### What is Kyber NVL1152?

It's a Kyber configuration that links [1,152 GPUs in one all-to-all NVLink domain](https://developer.nvidia.com/blog/nvidia-vera-rubin-pod-seven-chips-five-rack-scale-systems-one-ai-supercomputer/?ref=insidedeeptech.com) using direct optical rack-to-rack links. NVIDIA says Kyber is the foundation for Feynman scale-up.

## The bottom line

NVIDIA Feynman is a real roadmap commitment with a short list of confirmed ideas and almost no numbers. The ideas are big: stacked GPU dies, memory controllers inside HBM, a new Rosa CPU and an NVLink fabric that leaves the rack on light.

Watch three signals over the next year: whether NVIDIA puts numbers on Feynman at GTC 2027, whether TSMC's A16 hits volume in 2027, and whether Kyber ships on time with Rubin Ultra. For the generation right before Feynman, read Inside Deep Tech's [Rubin Ultra and Kyber full guide](https://www.insidedeeptech.com/nvidia-rubin-ultra-kyber-nvl576-full-guide/).