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# Hybrid Bonding: A Full Guide to Cu-Cu Stacking, SoIC, and Foveros Direct
- URL: https://www.insidedeeptech.com/hybrid-bonding-soic-foveros-direct-full-guide/
- Published: 2026-08-28T06:06:11.000Z
- Updated: 2026-08-28T06:06:11.000Z
- Description: Everything you need to understand hybrid bonding in 2026: why microbumps ran out of pitch, how Cu-Cu bonding works, TSMC SoIC vs Intel Foveros Direct, face-to-face density, and why 3D stacking is now a volume technology.
- Author: Austin Heaton
- Tags: Semiconductors, AI, Hardware

Hybrid bonding is not a transistor node, and it is not a synonym for "3D packaging." It is a die-to-die (or wafer-to-wafer) interconnect process: strip the solder microbumps, prepare copper pads and a dielectric surface, then bond copper to copper so two dies share a bumpless interface at single-digit-micron pitch. The product that ships is still a CPU, a GPU, an HBM stack, or an optical engine. The thing that changed is how those pieces talk vertically.

That split exists because microbumps ran out of pitch. For a decade, 3D stacks used solder microbumps in the 25–55 µm range — fine enough for early Foveros and HBM, too coarse for the bandwidth density AI and cache-on-logic now demand. At roughly 9–10 µm and below, solder geometry, underfill, and parasitics stop being a packaging detail and start being the bottleneck. Hybrid bonding deletes the solder. Copper pads meet copper pads. The joint looks more like an on-die via than a chip-to-chip link.

What changed in 2026 is not that hybrid bonding was invented. Sony put wafer-to-wafer Cu-Cu bonding into image sensors years ago; AMD's 3D V-Cache and Instinct MI300-class parts proved SoIC as a volume product; Intel published Foveros Direct pitches of 9 µm then 3 µm. What changed is that TSMC's SoIC roadmap now puts 6 µm pitches in high-volume manufacturing, face-to-face stacking in the customer mix, and A14-on-A14 SoIC targeted for 2029 — while Intel's [Foveros Direct](https://www.intel.com/content/www/us/en/foundry/library/advanced-process-technologies-for-data-center.html?ref=insidedeeptech.com) path pairs hybrid bonding with EMIB into 3.5D modules. The useful question is which stack is hybrid-bonded, which is still microbumped, and which slide is still a 2028 thermal argument.

This is the dedicated vertical-interconnect guide. Lateral 2.5D assembly — interposers, bridges, HBM shoreline — lives in the [TSMC CoWoS full guide](https://www.insidedeeptech.com/tsmc-cowos-packaging-full-guide/). Chiplet partition and die-to-die protocols live in [chiplets and UCIe](https://www.insidedeeptech.com/chiplets-ucie-full-guide/). Memory stacks have their own [HBM guide](https://www.insidedeeptech.com/high-bandwidth-memory-hbm-full-guide/). Optical engines that sit on SoIC-bonded PICs are covered in [co-packaged optics](https://www.insidedeeptech.com/co-packaged-optics-cpo-full-guide/). We do not re-derive them here.

### Key takeaways

- **Hybrid bonding is a Cu-Cu joint, not a foundry node and not "3D packaging" as a category.** Microbumps are solder. Hybrid bonds are copper pads fused through a dielectric face after surface activation. The pitch drops from tens of microns to single-digit microns. Density rises roughly with the square of that pitch shrink. [GAAFET](https://www.insidedeeptech.com/gaafet-nanosheet-transistors-full-guide/) decides how small the transistors are. Hybrid bonding decides how densely two dies can talk through the Z-axis.
- **TSMC SoIC and Intel Foveros Direct are the two named volume brands.** SoIC is TSMC's System on Integrated Chips 3D stack — SoIC-P (bumped) and SoIC-X (bumpless hybrid). Foveros Direct is Intel's solder-free successor to microbump Foveros, with first-generation copper bonding at 9 µm and a second generation at 3 µm per Intel Foundry's data-center technology page. Both can feed a 2.5D package afterward. Neither replaces CoWoS or EMIB.
- **Face-to-face beats face-to-back on density — when you can afford the thermal bill.** Broadcom-cited figures reported with TSMC's 2026 SoIC roadmap put face-to-back stacking near 1,500 signals/mm² (TSV-limited) versus about 14,000 signals/mm² for face-to-face hybrid copper bonding. That is an order-of-magnitude claim about interconnect density, not a free lunch on heat extraction from a logic-on-logic sandwich.
- **Pitch is the roadmap metric that matters.** TSMC's public SoIC path: \~9 µm in earlier volume (MI300-era), 6 µm in high-volume manufacturing as of mid-2026 commentary from TSMC advanced-packaging leadership, 4.5 µm targeted by 2029 with A14-to-A14 SoIC. Intel: 9 µm then 3 µm on Foveros Direct generations. Treat vendor dates as roadmap dates. Treat shipping SKUs (3D V-Cache, MI300/MI350-class, Clearwater Forest-class Xeon modules) as the existence proof.
- **Hybrid bonding composes with 2.5D; it does not replace it.** AMD's Instinct pattern is the canonical "3.5D": SoIC stack the compute/I/O vertically, then drop that object onto [CoWoS](https://www.insidedeeptech.com/tsmc-cowos-packaging-full-guide/) next to HBM. Intel's EMIB 3.5D does the horizontal job with bridges while Foveros Direct does the vertical. Confusing SoIC with CoWoS, or Foveros Direct with EMIB, is how a slide deck invents a bottleneck that is not the one you have.
- **The unsolved problem is not "can copper bond."** It is yield at finer pitch, known-good-die handling for die-to-wafer, warpage and overlay, thermal paths through a stack that no longer has solder or underfill as a compliance layer, tool capacity (bond aligners, plasma activation), and the fact that HBM itself is still largely microbump-bonded even as logic-on-logic goes hybrid. SK hynix and peers are pushing hybrid bonding toward later HBM generations; that is a memory roadmap, not a 2026 training-GPU default.

## Hybrid bonding at a glance

| Attribute                | Detail                                                                                                                                                                             |
| ------------------------ | ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- |
| What it is               | Direct copper-to-copper (plus dielectric) bonding between dies or wafers, without solder microbumps, at roughly sub-10 µm pad pitch                                                |
| What it is not           | A transistor node, CoWoS, EMIB, HBM as a product, UCIe as a protocol, or a drop-in for every 3D stack shipping in 2026                                                             |
| Core trick               | Replace solder joints with planar Cu pads so interconnect pitch — and therefore vertical bandwidth density — can scale like a back-end-of-line feature                             |
| Key hardware             | Copper pad / via arrays, dielectric bonding surface, plasma activation / surface prep, precision aligners, optional TSVs for face-to-back, temporary carriers                      |
| Transmission medium      | Micron-scale Cu-Cu bonds; signal path length measured in microns vertically, not millimeters laterally                                                                             |
| Main applications        | Cache-on-logic (3D V-Cache), logic-on-logic / logic-on-SRAM AI and CPU stacks, EIC-on-PIC optical engines (e.g. TSMC COUPE), future HBM hybrid stacks                              |
| Deployed today           | AMD 3D V-Cache and MI300/MI350-class SoIC; Intel Foveros Direct on advanced client/server modules; Sony-class CIS wafer bonds; TSMC SoIC at 6 µm HVM per 2026 packaging commentary |
| Biggest unsolved problem | Scaling pitch and face-to-face adoption without losing yield, known-good-die economics, or a thermal path a cold plate can actually clear                                          |

## What hybrid bonding actually is

Start with the thing it is not. It is not [CoWoS](https://www.insidedeeptech.com/tsmc-cowos-packaging-full-guide/). CoWoS places dies *side by side* on an interposer. Hybrid bonding places dies *on top of* each other. It is not EMIB. EMIB is a silicon bridge in a substrate for lateral bandwidth. It is not [UCIe](https://www.insidedeeptech.com/chiplets-ucie-full-guide/). UCIe is a die-to-die protocol and PHY family; hybrid bonding is how you might physically attach two dies that speak UCIe — or Infinity Fabric, or a proprietary cache bus. And "we use 3D packaging" on a slide does not tell you whether the joint is a 40 µm microbump or a 6 µm Cu pad.

A microbump joint is a solder ball (or copper pillar with solder cap) between two pads, underfilled, with a minimum pitch set by solder volume, shorting risk, and electromigration. Typical advanced packages lived for years in the 25–55 µm band. Intel's own Foveros Direct brief puts conventional microbump density against hybrid bonding and claims up to roughly 10× finer interconnect density once solder is gone and pitch drops into the sub-10 µm regime.

A hybrid bond is a planar process. Both surfaces carry copper pads set in a dielectric. Surfaces are cleaned and activated (often plasma). Dies or wafers are aligned. Thermocompression or related bonding forms a Cu-Cu joint and a dielectric-to-dielectric seal in one interface. There is no solder and, in the pure hybrid case, no traditional underfill. Electrical parasitics drop. Pitch can track copper pad lithography rather than solder ball geometry. The mechanical and thermal path becomes continuous metal and dielectric — which is good for conduction and unforgiving of particles, oxide, and overlay error.

Two geometries dominate the vocabulary:

**Wafer-to-wafer (W2W).** Two full wafers bond, then dice. Highest throughput when die sizes match. Bad economics when one die is scarce and the other is abundant — you scrap good die with bad partners.

**Die-to-wafer (D2W) / chip-on-wafer.** Known-good top dies land on a bottom wafer. Better yield economics for heterogeneous stacks. Harder alignment and handling. This is the path that matters for many logic-on-logic and EIC-on-PIC products.

Face orientation is a second fork. **Face-to-back (F2B)** stacks the front of one die on the back of another; signals often traverse TSVs in the lower die. **Face-to-face (F2F)** aligns active metal faces directly through hybrid bonds, skipping that TSV tax for the die-to-die bus. TSMC's second-generation SoIC emphasis on F2F is exactly this pitch-and-density argument. Heat still has to leave somehow. F2F does not invent a radiator.

## Why microbumps ran out of pitch

The congestion is geometric. Interconnect density scales roughly as 1/pitch². Move from 36 µm microbumps to 9 µm hybrid pads and you are in a different density class even before process details. Intel's Architecture Day-era Foveros Direct framing (widely cited in the packaging literature) put \~50 µm microbump pitch near 400 interconnects/mm² versus \~10 µm hybrid near 10,000/mm². Intel Foundry's current public language for Foveros Direct is sub-10 µm pitch and up to \~10× density versus conventional microbumps; the same data-center page states first-generation copper bonding at 9 µm and second generation at 3 µm.

Bandwidth and energy follow. A vertical Cu-Cu joint a few microns long is not a millimeter of organic trace or a fat microbump. Capacitance and resistance fall. That is why cache-on-compute and SRAM-on-logic show up first: the workload is latency- and bandwidth-sensitive, the die sizes can be matched, and the thermal stack (cache is cooler than a GPU front-end) is kinder than logic-on-logic.

HBM is the counter-example that keeps people honest. Today's HBM cubes are still largely microbump / TSV stacks sitting on a [CoWoS](https://www.insidedeeptech.com/tsmc-cowos-packaging-full-guide/) interposer next to the GPU. Hybrid bonding for HBM is a roadmap item among memory vendors — Hot Chips 2026 coverage had SK hynix discussing hybrid bonding timing relative to HBM4E/HBM5 — not the default joint under every 2026 training GPU. Do not read "hybrid bonding is shipping" as "every vertical interface in the AI package is hybrid."

## SoIC vs Foveros Direct vs "just hybrid bonding"

Vendor names are not physics. The physics is Cu-Cu. The names are process flows, customer models, and what you are allowed to put on top of what.

### TSMC SoIC

SoIC (System on Integrated Chips) is TSMC's 3DFabric vertical stack. TSMC's own SoIC materials describe ultra-high-density vertical integration intended to cut size and parasitics, with a SoIC assembly able to go subsequently into CoWoS, InFO, or System-on-Wafer. Public reporting around the 2026 North America Technology Symposium and follow-on packaging commentary puts the pitch path at roughly 9 µm → 6 µm (now in HVM) → 4.5 µm by 2029, with A14-to-A14 SoIC production targeted for 2029 at about 1.8× die-to-die I/O density versus N2-on-N2 SoIC. Face-to-face support is the second-generation capability that unlocks the Broadcom-cited jump toward \~14,000 signals/mm² versus \~1,500/mm² F2B.

AMD is the clearest volume customer story: 3D V-Cache on client/server CPUs, and Instinct MI300/MI350-class accelerators that SoIC-stack compute and I/O then ride CoWoS with HBM — the "3.5D" pattern. Broadcom's XDSiP work for Fujitsu Monaka is an early F2F SoIC-class design point (N2 compute on N5 SRAM in public descriptions), with volume aimed around 2027 and, notably, still discussed at 9 µm pitch in some coverage — innovators are not always first to the finest pitch.

### Intel Foveros Direct

Foveros began as microbump 3D (Lakefield, then Meteor Lake / Lunar Lake / Panther Lake client lines, Ponte Vecchio with EMIB). **Foveros Direct** deletes the solder. Intel's [Foveros Direct 3D technology brief](https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-11/foveros-direct-3d-tech-brief.pdf?ref=insidedeeptech.com) states sub-10 µm pitch via direct Cu-Cu hybrid bonding and up to \~10× interconnect density versus conventional microbumps. Intel Foundry's [data-center process page](https://www.intel.com/content/www/us/en/foundry/library/advanced-process-technologies-for-data-center.html?ref=insidedeeptech.com) is explicit on generational pitches: first generation at 9 µm, second at 3 µm. Clearwater Forest-class Xeon modules are the public vehicle that pairs Intel 18A compute chiplets, PowerVia, Foveros Direct, and EMIB 3.5D.

Intel's advantage is co-optimization with its own nodes and power delivery ([backside power / PowerVia](https://www.insidedeeptech.com/backside-power-delivery-powervia-full-guide/) sits in that same stack story). The trade for external foundry customers is a steeper qualification path than TSMC's merchant SoIC model. EMIB 3.5D — Foveros Direct modules linked laterally by EMIB — is Intel's answer to "3.5D" without a full CoWoS interposer.

### Everyone else

Samsung, OSATs (ASE, Amkor), and specialty bond-tool vendors (Besi, Applied Materials, TEL, and peers) all sit in the hybrid-bonding supply chain. For AI GPUs that still tape out at TSMC, SoIC-plus-CoWoS remains the gravitational center. For Intel-designed modules, Foveros Direct-plus-EMIB is the parallel stack. "Hybrid bonding" without a brand usually means the process physics; procurement still buys a named flow.

|                   | Microbump 3D (legacy Foveros / early stacks) | TSMC SoIC (hybrid)                              | Intel Foveros Direct                                          |
| ----------------- | -------------------------------------------- | ----------------------------------------------- | ------------------------------------------------------------- |
| Joint             | Solder microbump / Cu pillar + solder        | Cu-Cu hybrid (SoIC-X); SoIC-P is bumped cousin  | Cu-Cu hybrid                                                  |
| Pitch class       | \~25–55 µm typical                           | \~9 µm → 6 µm HVM → 4.5 µm (2029 target)        | 9 µm gen1 → 3 µm gen2 (Intel Foundry)                         |
| Density story     | Hundreds of joints/mm²                       | F2F cited \~14k signals/mm² vs \~1.5k F2B       | Sub-10 µm; up to \~10× vs microbump per Intel brief           |
| Typical next step | Package substrate / EMIB / CoWoS             | Often CoWoS or InFO ("3.5D")                    | Often EMIB 3.5D                                               |
| Proof points      | Meteor Lake-era Foveros; early HBM           | 3D V-Cache; MI300/MI350-class; COUPE EIC-on-PIC | Clearwater Forest / 18A module roadmap; Foveros Direct briefs |

## How hybrid bonding shows up in real products

**Cache on compute.** AMD 3D V-Cache is the volume existence proof most engineers have actually bought. An SRAM die hybrid-bonded (via SoIC) onto a CCD beats a larger monolithic cache on latency and binning economics. Thermal is manageable because the top die is memory.

**AI accelerators as 3.5D objects.** MI300-class parts stacked compute/I/O with SoIC, then placed that stack on CoWoS beside HBM. The hybrid bond is the vertical bus. The interposer is still how HBM and the second compute die share a package. Delete either sentence and the product description is wrong.

**CPU modules with active base tiles.** Intel's Foveros Direct framing puts compute chiplets on an active base tile (cache, fabric, power) at hybrid pitch, then tiles modules with EMIB. That is a different disaggregation style than "one giant CoWoS interposer," aimed at Xeon-class modularity and yield.

**Optical engines.** TSMC's COUPE path stacks an electronic IC on a photonic IC with SoIC-X hybrid bonding so the EIC–PIC interface is bumpless — covered in the [CPO guide](https://www.insidedeeptech.com/co-packaged-optics-cpo-full-guide/). Hybrid bonding here is a capacitance and density argument for modulators and TIAs, not a GPU cache argument.

**What is still not hybrid by default.** Most HBM stacks in 2026 AI packages. Many cost-sensitive 3D consumer parts. Anything whose pitch, yield, or thermal model still prefers microbumps. Hybrid bonding is winning the high-bandwidth vertical sockets first.

## Thermal, yield, and the boring constraints

Hybrid bonding removes solder compliance. That is a feature for electricals and a problem for mechanics. Particles become killer defects. Overlay and pad co-planarity dominate yield. Die-to-wafer needs known-good-die test that is good enough that you are not bonding expensive N2 logic onto scrap. Tooling — aligners, activation, metrology — is capacity-constrained industry-wide in the same qualitative sense CoWoS was, even if the monthly wafer numbers are not public in the same way.

Thermals are the other half. Face-to-face logic-on-logic puts two hot dies in intimate contact. Vendors prefer cache-on-logic and SRAM-on-compute first for a reason. Liquid cooling at package and rack level ([data center liquid cooling guide](https://www.insidedeeptech.com/data-center-liquid-cooling-ai-full-guide/)) is what makes dense 3D stacks shippable in AI halls; the bond process does not remove heat by itself. Intel markets continuous thermal paths as a Direct advantage versus solder; that is a conduction claim, not a free pass on cold-plate design.

Backside power complicates the stack drawing further. A die with [PowerVia / BSPDN](https://www.insidedeeptech.com/backside-power-delivery-powervia-full-guide/) has power on the back and signals on the front; F2B vs F2F and TSV strategies have to respect that. TSMC's 2026 SoIC public slides were called out as incomplete on backside-power permutations; Kevin Zhang's symposium comments (as reported) treated stacking on those nodes as supported even when the slide simplified. Treat "supported" as engineering, not as a shipping SKU list.

## A realistic timeline

| Horizon                 | What is actually happening                                                                                                                                                                                         | Confidence                                                           |
| ----------------------- | ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ | -------------------------------------------------------------------- |
| Now (2026)              | SoIC in volume for V-Cache and MI-class; \~6 µm SoIC HVM per TSMC packaging commentary; Foveros Direct on Intel's advanced module path (9 µm gen); COUPE-style EIC-on-PIC hybrid bonds; HBM still mostly microbump | High for shipping product classes; medium for exact pitch mix by SKU |
| Near term (2027–2028)   | More F2F SoIC customer designs (Monaka-class); finer SoIC pitches toward mid-single-digit µm; Foveros Direct 3 µm generation; selective hybrid HBM pilots                                                          | Medium — roadmap-tied                                                |
| Medium term (2028–2031) | A14-to-A14 SoIC (\~4.5 µm) targeted 2029; wider logic-on-logic if thermals allow; hybrid bonding deeper into HBM generations                                                                                       | Plausible on vendor dates; thermal/yield limited                     |
| Long term (2030s)       | Hybrid bonds as the default high-density vertical joint; microbumps relegated to cost-sensitive or coarse interfaces                                                                                               | Directional; year-level speculative                                  |

## The bottom line

2026 is the year hybrid bonding stopped being a specialty CIS and SRAM trick and became the vertical half of how leading AI and CPU packages are built — still beside, not instead of, CoWoS and EMIB.

The physics is old enough to be boring: delete solder, shrink pitch, raise interconnect density, cut joules per bit on the Z-axis. TSMC's SoIC and Intel's Foveros Direct are how that physics is productized, with 6 µm / 9 µm-class bonds in the volume conversation and 4.5 µm / 3 µm on the roadmaps. AMD's SoIC-plus-CoWoS accelerators and Intel's Direct-plus-EMIB modules are the two commercial patterns. Face-to-face is the density unlock; heat and yield are why not every stack uses it tomorrow morning.

For anyone making decisions today, the split is clean. If the question is how two logic or cache dies share a vertical bus at single-digit-micron pitch, you are in hybrid bonding. If the question is how those stacked objects sit next to HBM, you are back in [CoWoS](https://www.insidedeeptech.com/tsmc-cowos-packaging-full-guide/) or EMIB. If a vendor says only "advanced 3D packaging," ask: microbump or Cu-Cu, what pitch, F2F or F2B, and what 2.5D wrapper — if any — completes the package.

## Frequently asked questions

### What is hybrid bonding in semiconductors?

A packaging process that joins two dies or wafers by bonding copper pads (and surrounding dielectric) directly, without solder microbumps. It enables finer pad pitch and higher interconnect density than solder-based 3D stacking.

### How is hybrid bonding different from microbumps?

Microbumps use solder (often on copper pillars) at pitches typically measured in tens of microns. Hybrid bonding uses planar Cu-Cu joints at roughly sub-10 µm pitches, with lower parasitics and no traditional solder joint.

### What is TSMC SoIC?

System on Integrated Chips — TSMC's 3D stacking technology in the 3DFabric family. SoIC-X is the bumpless hybrid-bond variant. A SoIC stack can later be assembled into CoWoS or InFO as if it were one die.

### What is Intel Foveros Direct?

Intel's hybrid-bonding evolution of Foveros. Per Intel Foundry, first-generation Direct uses 9 µm copper bonding and second generation targets 3 µm. It is often combined with EMIB as EMIB 3.5D.

### Is hybrid bonding the same as CoWoS?

No. CoWoS is 2.5D (dies side by side on an interposer). Hybrid bonding / SoIC is 3D (dies stacked). They compose in "3.5D" products.

### Why does face-to-face matter?

F2F aligns active metal faces through hybrid bonds, avoiding much of the TSV path required in face-to-back stacks. Reported signal-density figures for F2F are about an order of magnitude higher than F2B in Broadcom/TSMC roadmap discussions (\~14,000 vs \~1,500 signals/mm²). Thermals remain the constraint.

### Is HBM hybrid-bonded today?

Most HBM in 2026 AI packages still uses microbump/TSV stacking. Memory vendors are developing hybrid-bonded HBM for later generations; do not assume the HBM cube next to a 2026 GPU is Cu-Cu hybrid throughout.

### Who ships hybrid bonding in volume?

Clear volume paths include AMD (SoIC for V-Cache and Instinct-class), Intel (Foveros Direct on advanced modules), TSMC (SoIC platform including optical-engine stacks), and historical CIS wafer bonding (Sony and peers). Exact wafer counts are not published as a tidy industry table.

## Methodology

This guide is based on primary and near-primary disclosures available as of 28 August 2026: Intel Foundry's Cutting-edge Process Technologies for Data Center page (Foveros Direct 3D copper bonding at 9 µm first generation and 3 µm second generation; EMIB 3.5D as Foveros Direct plus EMIB; Clearwater Forest / Intel 18A context); Intel's Foveros Direct 3D technology brief (PDF, Nov 2025 marking) stating sub-10 µm Cu-Cu hybrid bonding and up to \~10× interconnect density versus conventional microbumps; TSMC SoIC / 3DFabric positioning (SoIC as vertical stack subsequently assemblable in CoWoS/InFO/SoW; pitch and F2F roadmap items as reported from the 2026 North America Technology Symposium and subsequent packaging coverage, including \~6 µm HVM and 4.5 µm / A14-to-A14 targets for 2029 at \~1.8× I/O density vs N2-on-N2); Broadcom-cited F2B vs F2F signal-density figures (\~1,500 vs \~14,000 signals/mm²) as reported alongside that SoIC roadmap; AMD public product architecture for 3D V-Cache and Instinct MI300/MI350-class SoIC-plus-CoWoS ("3.5D") patterns; TSMC COUPE / SoIC-X EIC-on-PIC bonding as described in our co-packaged optics coverage and TSMC packaging materials. Absolute SoIC wafers-per-month, customer allocation shares, and SKU-by-SKU bond pitches are not fully disclosed by foundries and are labeled as roadmap or secondary reporting where used. Pitch numbers from vendors are process targets; shipping products may lag the finest published pitch.