> ## Content Index > Fetch the complete content index at: https://www.insidedeeptech.com/llms.txt > Use this file to discover other available public pages before exploring further. # Glass Core Substrates: A Full Guide to the Next Packaging Bottleneck After CoWoS - URL: https://www.insidedeeptech.com/glass-core-substrates-full-guide/ - Published: 2026-08-19T09:12:32.000Z - Updated: 2026-08-19T09:12:32.000Z - Description: Everything you need to understand glass core substrates in 2026: why ABF organic cores warp as CoWoS packages grow, what a through-glass via is, Intel’s EMIB-on-glass demos versus Absolics samples, and why this is not CoWoS. - Author: Editorial Team - Tags: Semiconductors, AI, Hardware A glass core substrate is not a transistor, not a foundry node, and it is not [CoWoS](https://www.insidedeeptech.com/tsmc-cowos-packaging-full-guide/). It is a package substrate whose *core* — the stiff middle of the board the dies sit on — is a sheet of glass instead of an organic laminate. Through-glass vias replace the plated through-holes of a BT/ABF core. Build-up films still go on both faces. The product the customer buys is still a BGA. The thing that changed is the material that has to stay flat while two reticle-sized compute dies and eight [HBM](https://www.insidedeeptech.com/high-bandwidth-memory-hbm-full-guide/) stacks go through reflow. That change exists because the organic answer is running out of geometry. Ajinomoto Build-up Film on an organic core has carried every serious CPU and GPU package for a quarter-century. It warps as the body grows. It has a coefficient of thermal expansion far from silicon. Its through-holes do not scale like the bump maps that [chiplets](https://www.insidedeeptech.com/chiplets-ucie-full-guide/) and HBM now demand. Intel said as much in September 2023: by the end of the decade, organic materials hit their limit on shrinking and warping, and glass is the next core. TSMC's chairman said the complementary thing on 16 July 2026: today's majority is still CoWoS; glass is a cost-down alternative on a pilot line that needs about another year before it can go into production with a customer. What changed in 2026 is not that glass packaging was invented. Corning, AGC, IBM, and Georgia Tech published through-glass-via interposers more than a decade ago. It is that Intel Foundry has now shown a 10-2-10 glass-core panel with copper-filled vias and embedded EMIB bridges that survive thermal shock without the edge-crack defect the industry calls SeWaRe; that Absolics has sent Georgia-made samples to Taiwan for package-level reliability; and that TSMC is building a panel-level line whose glass story is easy to confuse with a glass-core substrate and is not the same object. The useful question is which of those is a core, which is an interposer, which is a carrier, and which of them is on a 2026 bill of materials. None of them is, as a volume SKU. CoWoS still is. ### Key takeaways - **A glass core replaces the organic *core* of a package substrate. It is not CoWoS, and it is not a glass interposer.** CoWoS is TSMC's 2.5D flow: dies and HBM on an interposer, then that sandwich on a substrate. Glass core is a candidate for that last board, or for Intel's EMIB substrate. A glass *interposer* would replace the silicon or RDL interposer. A glass *carrier* is a panel the dies are parked on during assembly. Vendor slides flatten the three. - **Organic ABF cores are hitting warpage and via-density limits, not a chemistry deadline.** Silicon sits near 2.6–3.2 ppm/K. Organic cores sit closer to 12–17 ppm/K in plane. As CoWoS-L packages grow from 3.5× to 5.5× reticle, and as TSMC sketches 14× for 2028, that mismatch shows up as yield and C4 reliability. Glass can be formulated closer to silicon. That is the mechanical argument. It is not a 2026 drop-in. - **The via is the product.** Through-glass vias (TGVs) are laser- or etch-formed holes, copper-filled, that play the role plated through-holes play in organic cores and TSVs play in silicon interposers. Intel's 2023 numbers: <5/5 µm line/space on the build-up, <100 µm TGV pitch, die-to-die bump pitch under 36 µm. AGC will drill 20–150 µm holes in EN-A1 glass on 300 mm wafers *or* 510 × 515 mm panels. Filling those holes without voids, then dicing the panel without edge cracks, is the yield problem. - **Intel has the deepest public process story. Absolics has the first dedicated factory. Neither is high-volume manufacturing.** Intel's September 2023 newsroom piece committed complete glass-substrate solutions in the second half of this decade. ECTC 2026 and NEPCON Japan 2026 are demonstration hardware: a 10-2-10 stack, fully filled TGVs, two embedded EMIB bridges, a 510 × 515 mm panel, no SeWaRe after harsh thermal shock. Absolics (SKC) has a Covington, Georgia plant backed by CHIPS money; NIST's own award page still says first deliveries in 2025 and production capacity in 2027\. SKC's July 2026 call put embedded samples into package-level eval in Taiwan. That is qualification. It is not a GPU SKU. - **TSMC's glass work is a CoWoS cost-down, not a 2026 substitute.** C.C. Wei, Q2 2026: the majority is still CoWoS; they are developing an alternative to lower cost; they work with a substrate vendor; the pilot line needs about another year to mature before production with a customer. Do not merge a glass carrier, a glass core, and a glass interposer because the slide says "glass." - **2026–2030 is samples, then first customer production, then — if dicing and reliability hold — HVM.** Treat 2027–2028 as the earliest honest window for a named product on glass core. Treat 24 × 24 cm systems-in-package and a trillion transistors on a package as Intel's 2030 ambition, not a 2027 forecast. A Blackwell-class GPU in 2026 still leaves on organic. ## Glass core at a glance | Attribute | Detail | | ------------------------ | --------------------------------------------------------------------------------------------------------------------------------------------------------- | | What it is | A package substrate whose core is glass, with copper-filled through-glass vias and organic (often ABF) build-up on both faces | | What it is not | CoWoS, a silicon interposer, a glass interposer, a glass carrier wafer, a 2026 GPU bill of materials, or a replacement for HBM | | Core trick | Match silicon's CTE, stay flat at large body size, and punch denser vertical vias than an organic core will allow | | Key hardware | Glass panel (wafer or 510 × 515 mm class), TGVs, build-up RDL, optional embedded silicon bridges (EMIB) or cavities for passives, C4/BGA | | Transmission medium | Copper in glass vias and in build-up; not optical by default, though Intel has co-formed waveguides in the same panel | | Main applications | Large AI/HPC multi-chiplet packages, later graphics; RF and glass IPD are a separate, older TGV market | | Deployed today | Test vehicles, panel demos, customer samples and package-level quals. No high-volume AI GPU on glass core in 2026 | | Biggest unsolved problem | Forming, filling, and *singulating* TGV panels at yield — SeWaRe (edge cracks), void-free copper, and board-level reliability on bodies that keep growing | ## What a glass core actually is The three-way mix-up is the whole story, so keep the nouns. A glass *core* is the middle of the BGA substrate — a candidate for the last "S" in CoWoS, or for Intel's EMIB board. A glass *interposer* would sit under the dies at silicon-like density (AGC sells EN-A1 for that; Samsung/Rapidus have been reported on it). A glass *carrier* is a process panel. Analysts who parse Wei's July 2026 answer — "alternative to lower the cost" plus "work with a substrate vendor" — split those into a carrier (CoP) and a core (oS). That split is analysis. TSMC's transcript does not name CoPoS. Intel's version is more specific still: put the glass under [EMIB](https://www.insidedeeptech.com/chiplets-ucie-full-guide/) silicon bridges so you keep dense die-to-die wiring without a reconstructed interposer wafer. What remains is a sandwich. A typical advanced organic substrate is described as N-2-N: N build-up layers, a two-layer core, N more build-up layers. Intel's ECTC 2026 vehicle is a 10-2-10: ten redistribution layers, a two-layer *glass* core with fully copper-filled TGVs, ten more layers. The build-up can still be ABF or a cousin. Glass does not retire Ajinomoto. It retires the woven-glass/epoxy (or BT) *core* that ABF has been hanging from. Ming-Chi Kuo's later CoPoS note makes the same sandwich point from the TSMC side: glass and ABF are complementary, not substitutes. Treat that as a useful heuristic, not as a TSMC datasheet. ### Through-glass vias A TGV is a hole through the glass, metallized, usually copper-filled. Functionally it is the cousin of a plated through-hole in an organic core and of a TSV in a silicon interposer. The process is not the same. Glass is an insulator, so you do not need the liner dielectric a TSV requires before copper. That is a real cost and RF argument, and it is why glass showed up in RF interposers and integrated passive devices years before anyone put a GPU on it. The AI-package argument is density and mechanics, not Wi-Fi. Intel's September 2023 [newsroom disclosure](https://newsroom.intel.com/artificial-intelligence/intel-unveils-industry-leading-glass-substrates?ref=insidedeeptech.com) is the right public spec sheet for the ambition: 50% less pattern distortion than organic, ultra-low flatness for lithography depth of focus, a claimed 10× interconnect-density increase, ability to integrate optical interconnects and to embed inductors and capacitors at higher process temperatures. Tom's Hardware's write-up of the same briefing, which matches Intel's accompanying slides, put numbers on the design rules: <5/5 µm line/space, <100 µm TGV pitch, die-to-die bump pitch <36 µm, core bump pitch <80 µm. The 2023 test chip used 75 µm TGVs at a 20:1 aspect ratio in a 1 mm core. Those are demonstration rules. They are not a 2026 production design guide. AGC's current [TGV product page](https://www.agc.com/en/products/electoric/detail/tgv.html?ref=insidedeeptech.com) is the merchant version of the same physics. EN-A1 is a non-alkali glass, CTE close to silicon, offered as 150/200/300 mm wafers *and* as 510 × 515 mm panels, 0.1–1.0 mm thick, through or blind vias, straight/taper/hourglass, 20–150 µm diameter. That 510 × 515 mm panel size is not a coincidence. It is the same envelope Intel later showed as a 24-layer glass-core panel at ECTC 2026\. The materials companies got to panel scale before the IDMs got to a shipping processor. ### CTE, warpage, and why silicon cares Silicon's coefficient of thermal expansion is about 2.6–3.2 ppm/K. Copper is about 17\. Organic cores, depending on the resin and the weave, typically land in the low-to-mid teens in plane and much higher out of plane. A large silicon die (or two, plus HBM cubes whose own silicon is also \~3 ppm/K) on an organic substrate is a bimetallic strip every time the package sees reflow, test, or a power cycle. Warpage during Chip-on-Wafer and Wafer-on-Substrate is already a CoWoS yield term. It gets worse as the body grows. Glass is not magically "zero CTE." It is *tunable*. Alkali-free boro-aluminosilicate formulations used for interposers and cores are specified to sit near silicon. That is AGC's reliability claim and Intel's mechanical claim. A closer CTE match does three things: less warpage at large body size, better overlay from layer to layer in the build-up (Intel's ECTC 2026 paper reports a significant overlay improvement versus organic core), and less strain energy in the C4 joints. TSMC's own CoWoS-R page already treats the RDL/C4/underfill stack as a CTE *buffer* between SoC and organic substrate. Glass tries to shrink the mismatch at the source. The catch is brittleness. Organic cores forgive handling. Glass does not. Every subsequent section of this guide is some version of that sentence. ### Panel versus wafer Organic substrates are already a panel business. Silicon interposers are a wafer business: round 300 mm, reconstructed, diced. Glass can be either. That is the manufacturing fork. - **Wafer.** 300 mm round. Fine for RF TGV and process development; poor utilization once the package is a large rectangle. - **Panel.** 510 × 515 mm in the Intel/AGC class; 310 × 310 mm in the CoPoS-class numbers around TSMC Chiayi AP7\. Better utilization, different tools. Intel's ECTC 2026 abstract is explicit that the 10-2-10 parts were built at panel scale *on traditional organic substrate lines* and then diced. That is the 1990s ceramic-to-organic bet again: reuse the installed base. It is also why Absolics' factory and TSMC's pilot can both be "true" without being the same product. ## Why organic cores are the next bottleneck after CoWoS [CoWoS](https://www.insidedeeptech.com/tsmc-cowos-packaging-full-guide/) solved the problem of getting two reticle-limited dies and eight HBM stacks onto one interposer. It did not retire the organic substrate underneath. As the interposer grows — TSMC is in production on 5.5× reticle CoWoS in 2026 and has a 14-reticle sketch for 2028, about ten large compute dies and twenty HBM stacks — the board it sits on has to stay flat, keep power, and escape SerDes. That board is still, in volume, an ABF build-up on an organic core from the usual Japanese and Taiwanese substrate makers. Three limits show up at once. **Warpage.** A 5.5× interposer is already a large, thin, CTE-mismatched sandwich. 14× is a substrate with a science project on it. Organic cores shrink, twist, and hog as they see heat. Assembly yield is a warpage number long before it is a transistor number. **Via density and design rules.** Plated through-holes in an organic core do not track the bump pitches HBM4/HBM4e and UCIe want. Intel's 2023 claim of a 10× interconnect-density step is a design-rule claim about what glass *allows*, not a measurement on a shipping GPU. The direction is not controversial. The year you can buy it is. **Body size.** Intel's 2023 briefing talked about 24 × 24 cm systems-in-package and a trillion transistors on a package by 2030\. That is a panel, not a CoWoS-S interposer. Organic cores have been pushed toward large bodies in networking ASICs; they have not been asked to do it under a dual-reticle GPU plus a ring of [HBM](https://www.insidedeeptech.com/high-bandwidth-memory-hbm-full-guide/) at 2026 power densities. CoWoS is the 2026 chokepoint. Glass is the material bet for when those packages outgrow the organic board they land on — or, at Intel, for growing EMIB without a reconstructed interposer wafer. It is a 2027–2030 problem being qualified in 2026\. It is not a substitute for a CoWoS slot this year. ## How this relates to CoWoS — and how it does not A short mapping, because the slides will not provide one. | Object | Job | 2026 volume? | Glass version | | -------------------------------------------- | -------------------------------------------------------------- | ------------------------------------- | --------------------------------------------------------------------------------------------------------------------------------------------- | | CoWoS-S/L/R interposer | Dense die-to-die and die-to-HBM wiring under the compute | Yes — this is the AI GPU line | A *glass interposer* would compete here. That is not what Intel is showing. TSMC has not said it is replacing CoWoS-S silicon with glass | | Organic package substrate (the "S" in CoWoS) | Power, SerDes escape, BGA, mechanical | Yes | **Glass core substrate.** This is the Intel/Absolics product. TSMC says it is working with a substrate vendor | | EMIB / EMIB-T | Silicon bridges in an organic (today) substrate | Intel products; not NVIDIA's 2026 GPU | **EMIB in glass core.** Intel's 2026 demos. Two bridges in the NEPCON/ECTC vehicles | | CoPoS panel | Chip-on-panel instead of chip-on-wafer, to escape round 300 mm | Pilot | May use a glass *carrier* or panel. Not the same as a glass-core BGA. Trade press puts Chiayi AP7 on \~310 × 310 mm; volume talk is 2028–2029 | | SoIC / hybrid bond | 3D stack, then dropped into CoWoS | Limited, growing | Orthogonal. Glass does not replace hybrid bonding | NVIDIA's 2026 flagship GPUs are still a TSMC 4NP + CoWoS-L object on an organic substrate. Intel's glass+EMIB demos are a foundry packaging roadmap. Both can be true. The mistake is to read a NEPCON booth as a Blackwell second source. Optical is the one place the objects overlap in a technically interesting way. Intel's ECTC 2026 work co-formed electrical TGVs and optical waveguides in the same glass. That is a [co-packaged optics](https://www.insidedeeptech.com/co-packaged-optics-cpo-full-guide/) story — glass as a photonic platform as well as a power-delivery platform — and it is research-grade in 2026\. TSMC's COUPE-on-CoWoS path does not require a glass core to ship a 2026 switch. Do not wait for glass to get CPO. Do not ignore that glass is one of the few package materials that can carry both. ## Intel: a decade of research, a 2026 demo, not a SKU Intel's public clock starts on 18 September 2023\. After "a decade of research," the company announced [one of the industry's first glass substrates for next-generation advanced packaging](https://newsroom.intel.com/artificial-intelligence/intel-unveils-industry-leading-glass-substrates?ref=insidedeeptech.com), planned for the latter part of this decade, with complete solutions in the second half of the decade so the industry can keep scaling beyond 2030\. Babak Sabi, then SVP of assembly and test, is the named executive. First markets: data center, AI, graphics — the large-body workloads. The trillion-transistor-on-a-package line is in the same release. PowerVia and RibbonFET are name-checked as sibling "beyond 18A" bets, which is packaging marketing sitting next to the [GAAFET](https://www.insidedeeptech.com/gaafet-nanosheet-transistors-full-guide/) node, not a claim that 18A ships on glass. 2024–2025 was the rumor window. Key-employee departures produced a "Intel killed glass" cycle. The company did not publish a kill notice. It also did not name a first production processor. The defensible statement through 2025 was: program continues, second half of the decade, no SKU. 2026 is the demo year. **NEPCON Japan, 22 January 2026.** Intel showed what it called the first sample combining a thick-core glass substrate with EMIB. Trade-press descriptions of the booth (Wccftech and others working from the same material) put a 10-2-10 stack on the table, two embedded EMIB bridges, a package on the order of 78 × 77 mm — roughly two reticle fields of silicon — and bump pitch down to 45 µm, with a No SeWaRe claim in testing. That is a diced *package*, not the mother panel. **IEEE ECTC 2026.** The paper to read is *Glass Core Substrates – Next Generation Advanced Packaging Platform for AI and HPC* (IEEE 11561301). The abstract, which is the part that is public without a paywall, is specific: low-taper, fully copper-filled, void-free TGVs that withstand TSC750 thermal shock with no defects or glass cracking; first-time 10-2-10 thick glass cores with filled TGVs *and* embedded silicon bridges (EMIB); manufactured at panel scale on traditional organic-substrate lines, then diced; diced units show no SeWaRe after the same thermal-shock class; significant RDL overlay improvement versus organic core; successful co-formation of electrical TGVs and optical waveguides; a 510 × 515 mm, 24-layer glass-core panel with filled TGVs and two EMIBs was the large prototype on the booth. Intel Foundry's own ECTC recap (Lori Scott, 5 June 2026) repeats the TGV flexibility claim — low-taper, mixed sizes, cavities for embedding devices — and the warpage/overlay argument. SemiAnalysis's ECTC 2026 notes add the OSAT counterpoint, which Intel's abstract does not: STATS ChipPAC's 74 × 74 mm glass-core packages failed every test segment *without* edge coating; edge-coated parts completed assembly and reliability, with 33.5% less warpage. Amkor and STATS measured 30–40% lower substrate-level warpage than organic references, with assembly defects and TGV-fill problems still showing an immature process. That is the right 2026 score: Intel can make a panel that dices without SeWaRe in its own flow; the OSAT ecosystem is not yet a cookbook. What Intel has not done, as of 19 August 2026, is name the first production CPU, GPU, or foundry customer SKU, or a volume quarter. "Second half of this decade" is still the clock. A 2026 demo that survives TSC750 is necessary. It is not a tape-out. ## Absolics: a factory in Georgia, samples in Taiwan Absolics is SKC's US glass-substrate subsidiary, not an Intel division. The two programs are constantly fused in social posts because both say "glass substrate" and because SK Group and Intel have other relationships. A dedicated guide should not fuse them. Intel's glass work is a vertically integrated foundry packaging flow with EMIB. Absolics is a merchant substrate supplier trying to sell panels and cores into someone else's assembly line. The factory is real. NIST's [CHIPS award page](https://www.nist.gov/chips/absolics-georgia-covington?ref=insidedeeptech.com) is the primary source: up to $75 million in direct funding, Covington, Georgia, 120,000 square feet, expected capital expenditure $343 million, glass substrates for advanced packaging, first deliveries to customers expected in 2025, production capacity expected to kick in 2027\. A later Commerce award added another $100 million for a glass-core packaging ecosystem and R&D around that low-volume plant (NIST Absolics Inc. / SMART Packaging). The plant's existence is not the dispute. The dispute is whether "production capacity in 2027" survives customer qualification. It has already slipped once. SKC originally talked mass production in 2024, then 2025\. Korean coverage in 2026 (Korea Herald, The Elec, local filings) is consistent on the shape: SKC sold other businesses to concentrate on glass; a 1.17 trillion won raise sent a large share to Absolics; the company has at times declined to specify a mass-production date in official materials. Treat 2027 as the NIST award timeline and as a *capacity* date, not as a sold-out GPU substrate date. The July 2026 snapshot is more useful than the 2024 slides. On SKC's 27 July 2026 earnings call, as reported by The Elec, embedded glass-substrate samples from the Georgia plant had been sent to Taiwan and package-level reliability evaluation had begun — electrical, thermal, mechanical, on an actual package, which is the last technical gate before a customer proof-of-concept. SKC said it had good-die samples. It aimed to move into PoC with customers after those evals, with feedback possibly this year. A separate *non-embedded* glass-substrate track with multiple global customers was expected to see supplier selections in the second half of 2026 and PoC after that. Embedded is the ambitious version: passives in the glass, package height claims on the order of 3.9 mm down to 1.8 mm in company language. Non-embedded is the simpler core swap. The fact that Absolics is running both is a tell. Customers are not all buying the science-project stack. AMD-as-customer and AWS-as-customer appear in trade press. They are not in the NIST page and not in an Absolics 8-K we can point at. Label them as reporting. Do not write "Absolics is qualifying AMD" as a fact. ## TSMC, Samsung, IBM, AGC: who is actually doing what **TSMC.** Primary source: C.C. Wei on the [16 July 2026 earnings call](https://investor.tsmc.com/english/encrypt/files/encrypt%5Ffile/reports/2026-07/547d1696765e05ce3adb81c108ce1c8c1682b80c/TSMC%202Q26%20Transcript.pdf?ref=insidedeeptech.com). Analyst question on glass-core / glass-substrate / glass-carrier progress, given the 14× CoWoS roadmap and a Japan symposium substrate demo. Wei: today the majority is still CoWoS; TSMC is developing that alternative to lower cost; TSMC also works with a substrate vendor so the customer can have product in the market; they are building a pilot line announced a few quarters ago; it takes about another one year to be mature so they can put it into production with the customer. That is the whole quote. It does not say CoPoS. It does not say 510 × 515\. It does not say 2028\. It does not say NVIDIA. Everything else — Chiayi AP7, 310 × 310 mm panels, VisEra mini-line, 2028–2029 volume, glass core after 2030 — is Commercial Times, TrendForce, or sell-side. Some of it will be right. Cite Wei for what TSMC will defend, and the rest as analysis. CoWoS remains the 2026 product. Glass is a parallel, cost-down, not-yet-mature line. **Samsung.** SEMCO has a glass-substrate program that Korean trade press has described as delayed — slipped reliability, 2028-or-later gossip. Samsung Foundry's packaging brands remain I-Cube / H-Cube. There is no Samsung newsroom equivalent of Intel's 2023 commitment. "Samsung is in the race" is accurate. "Samsung HVM in 2027" is not a primary source. **IBM.** IBM Research, often with Corning, published some of the earliest TGV-interposer process papers (ECTC-era copper-filled vias in thin fusion-draw glass). That is why the industry believes the via can be a manufacturing process. It is not a 2026 IBM product line. Current IBM packaging talk is silicon bridges; glass remains a materials-and-university thread (SRC/CHIMES). Credit as an origin, not a merchant. **AGC and Corning.** AGC sells EN-A1: non-alkali, CTE near silicon, 300 mm wafers and 510 × 515 mm panels, 20–150 µm vias, for packaging, glass interposers, 3D glass IPD, MEMS. Corning sells carrier and TGV glass on the same pitch. Neither assembles a GPU. SCHOTT sits in the same materials tier. A shared 510 × 515 mm outline is the supply chain rhyming, not a design win. **Everyone else.** AT&S has a Leoben glass-core R&D center under IPCEI. Rapidus appears in industry maps as a later glass-interposer name. 3D Glass Solutions is RF/IPD, not an Absolics analogue. OSATs (Amkor, STATS ChipPAC, ASE) are in assembly trials; STATS' edge-coating result is the public reliability datapoint that is not Intel's. ## What still breaks: SeWaRe, fill, and dicing The 2026 literature has a villain with a name. **SeWaRe** is the edge-crack / micro-crack signature that shows up when you singulate a metallized glass panel — a saw, a laser, a combination — and the residual stress in the copper-filled vias and the build-up lets go at the edge. Intel's claim at NEPCON and in the ECTC abstract is that diced 10-2-10 parts show *no* SeWaRe after TSC750-class thermal shock, including after two-sided dielectric pull-back. STATS ChipPAC's claim is that a 74 × 74 mm body without edge coating failed every test segment, and that edge coating plus build-up pull-back is becoming a requirement. Both can be true. Intel's flow is not yet the industry's flow. The other failure modes are older: - **TGV formation.** Laser-induced deep etching (LPKF LIDE and cousins), wet etch, and hybrids. Taper, roughness, and microcracks in the via wall decide whether copper will fill and whether the glass will survive. - **Copper fill.** Void-free, through a high-aspect-ratio insulator, without cracking the glass on cooldown (copper wants to shrink more than glass). Intel says it has this on the 10-2-10\. OSAT notes still mention fill problems. - **Handling and dicing.** DISCO and others have shown multiple glass-substrate dicing methods. None is as forgiving as sawing organic. - **Board-level reliability.** Package-level thermal shock is necessary. Drop, bending, and a lead-free reflow profile on a 100 mm-class body are the tests customers actually buy. Absolics' Taiwan eval is this gate. - **Inspection.** Glass is transparent, which helps. TGV voids and SeWaRe still want dedicated metrology (the KLA/Onto names in the tool papers). Until those five are boring, glass core is a qualification program. [EUV](https://www.insidedeeptech.com/euv-lithography-asml-machines-full-guide/) Low-NA is a factory; High-NA is the argument. Glass is not a factory. ## A realistic timeline | Horizon | What is actually true | Confidence | | ----------------------- | ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | ------------------------------------------------------------------ | | Now (2026) | Organic ABF cores remain the volume substrate under CoWoS and under EMIB. Intel: 10-2-10 glass+EMIB panels and diced packages, no SeWaRe in its thermal-shock flow, optical waveguides co-formed. Absolics: Georgia samples in Taiwan package-level eval; non-embedded PoCs aimed this year. TSMC: CoWoS majority; glass/panel pilot \~1 year from "mature enough to produce with a customer." AGC/Corning selling TGV glass, including 510 × 515 mm panels | High — newsroom, ECTC abstract, NIST, TSMC transcript, AGC catalog | | Near term (2027–2028) | First customer production *possible* if Intel's "second half of the decade" and NIST's Absolics 2027 capacity date both hold. TSMC pilot maturity \~2H 2027 by Wei's "another year" from July 2026; that is a mature *pilot*, not a sold-out line. CoPoS volume in trade press 2028–2029\. SEMCO still a 2028-or-later rumor | Medium — dates exist; no named SKU | | Medium term (2028–2031) | Honest HVM window *if* SeWaRe, fill, and board-level reliability are cookbook. Glass core under some large AI/HPC packages, still next to CoWoS-L (or EMIB-T) rather than instead of them. 14-reticle CoWoS in 2028 does not require glass; it makes glass more interesting | Plausible on current roadmaps; yield-limited | | Long term (2030s) | Intel's 24 × 24 cm SiP and trillion-transistor package; glass as a photonic+electrical substrate; organic cores remaining on everything that does not need the body size. Or glass stays a niche because edge coating, fill, and cost never beat a better organic | Speculative. 2023 ambition, not a forecast | One useful heuristic: ask whether the glass is a *core*, an *interposer*, or a *carrier*; whether the vias are filled; whether the part has been diced without SeWaRe; and whether a customer has finished package-level reliability. Do not ask whether a company "supports glass substrates." ## The bottom line 2026 is the year glass core substrates stopped being a 2013 ECTC poster and became a panel you can photograph at NEPCON — and the year they still did not become a GPU. The physics is old. Silicon and HBM want a core whose expansion looks like silicon, whose vias are denser than a plated through-hole, and whose body can grow past the point where organic warpage eats the assembly yield. Intel has now built that sandwich with EMIB inside it and shown that, in its own flow, the diced parts do not crack at the edge under harsh thermal shock. Absolics has a factory in Georgia and samples in a Taiwan reliability queue. TSMC will spend the next year making a pilot line mature enough to run with a customer while CoWoS continues to gate the actual accelerators. AGC will sell you the glass either way. For anyone making decisions today, the split is clean. If the question is what sits under a 2026 training GPU, you are looking at [CoWoS](https://www.insidedeeptech.com/tsmc-cowos-packaging-full-guide/)\-L, [HBM](https://www.insidedeeptech.com/high-bandwidth-memory-hbm-full-guide/), and an organic substrate. If the question is what has to change when that package is 14 reticles and the organic core is the thing that warps, you are looking at glass core — Intel's EMIB version, Absolics' merchant version, or a TSMC substrate-vendor version — on a 2027–2030 clock. If the question is whether a booth demo of filled TGVs is a product, it is not. The demo is how you get to the product. The product is a diced, qualified, high-yield panel on a named SKU. That SKU has not been named. ## Frequently asked questions ### What is a glass core substrate? A package substrate whose central core is a glass panel rather than an organic laminate, with copper-filled through-glass vias and build-up wiring (often still ABF) on both faces. It is the board a multi-die AI package would sit on, not the transistors and not the CoWoS interposer. ### How is this different from CoWoS? CoWoS is TSMC's 2.5D assembly: chips on an interposer, then on a substrate. Glass core is a candidate for that substrate (or Intel's EMIB substrate). A 2026 NVIDIA GPU uses CoWoS on organic. ### How is a glass core different from a glass interposer or a glass carrier? A core is the middle of the BGA substrate. An interposer sits directly under the dies at wiring densities closer to silicon (today usually silicon or RDL). A carrier is a process panel used during assembly. TSMC's CoPoS talk mixes panelization with glass; it is not automatically a glass-core BGA. ### Why can't organic ABF substrates just get bigger? They can, and they have. Warpage, CTE mismatch (\~3 vs \~12–17 ppm/K), and through-hole density get worse at 5.5× and 14× reticle-class bodies with many HBM stacks. Organic is the 2026 volume answer. It may not remain the large-body answer. ### What is a through-glass via (TGV)? A metallized hole through the glass core, usually copper-filled, connecting the top and bottom build-up. Analogous to a plated through-hole in organic or a TSV in silicon, without a TSV's liner dielectric because glass is already an insulator. ### What is SeWaRe? The named edge-crack defect on singulated glass substrates. Intel's 2026 vehicles claim none after thermal shock. Independent OSAT work has required edge coating and build-up pull-back to get a 74 × 74 mm body through reliability. It is the dicing-and-stress problem, not a via-drill problem. ### Is Intel using Absolics glass? Not as a stated fact. Intel has a decade-long in-house glass-core program and demonstrated EMIB-in-glass in 2026\. Absolics is an SKC merchant supplier with a CHIPS-funded Georgia plant sending samples to Taiwan. They are the two most visible programs. They are not, on the public record, the same program. ### When will glass core substrates be in high-volume manufacturing? Intel: second half of this decade, no SKU named. Absolics/NIST: production capacity in 2027, with package-level quals running in 2026 after earlier slips. TSMC: pilot about a year from July 2026 to maturity, then production with a customer; CoWoS remains the majority. Honest HVM for a named AI package is a 2028–2030 question, not a 2026 one. ### Will glass replace CoWoS? No. At most it changes the substrate CoWoS lands on, or it grows as Intel's EMIB path, or it appears as a panel-level (CoPoS) flow that is a cousin of CoWoS rather than a kill shot. Wei's own words: today's majority is still CoWoS. ### Does glass core help HBM? Indirectly. More HBM stacks need more shoreline and a flatter, larger package. Glass does not replace the HBM cube or the CoWoS-L bridge that talks to it. It is one of the materials that might let you place twelve or twenty stacks without the organic core becoming the yield limiter. ## Methodology This guide is based on primary company, government, and conference disclosures available as of 19 August 2026: Intel's 18 September 2023 newsroom announcement "Intel Unveils Industry-Leading Glass Substrates to Meet Demand for More Powerful Compute" (latter part / second half of this decade, 10× interconnect density, 50% less pattern distortion, optical and embedded-passive language, first use in large-body data center/AI/graphics, trillion transistors on a package by 2030); IEEE ECTC 2026 paper *Glass Core Substrates – Next Generation Advanced Packaging Platform for AI and HPC* (IEEE 11561301) abstract (10-2-10 thick glass core, fully copper-filled void-free TGVs surviving TSC750, embedded EMIB, panel-scale manufacture on organic-substrate lines, no SeWaRe after dicing and thermal shock, RDL overlay improvement, co-formed optical waveguides); Intel Foundry's 5 June 2026 ECTC recap; TSMC Q2 2026 earnings call transcript, 16 July 2026, C.C. Wei on glass-core/glass-substrate/glass-carrier (CoWoS still the majority, cost-down alternative, work with a substrate vendor, pilot line \~one more year to mature before production with a customer); NIST CHIPS page for Absolics (Georgia), Covington plant, up to $75 million, $343 million expected capex, first deliveries 2025, production capacity 2027; AGC Through Glass Vias product page (EN-A1, 300 mm wafers and 510 × 515 mm panels, 0.1–1.0 mm, 20–150 µm vias). NEPCON Japan 22 January 2026 booth details (10-2-10, \~78 × 77 mm diced package, 45 µm bump pitch, two EMIBs, No SeWaRe) are from contemporaneous trade-press coverage of Intel's sample, not from a numbered Intel datasheet. STATS ChipPAC 74 × 74 mm edge-coating results and Amkor/STATS warpage ranges are from ECTC 2026 reporting (SemiAnalysis), not from those OSATs' investor filings. SKC/Absolics July 2026 Taiwan package-level evaluation and dual embedded/non-embedded PoC tracks are from The Elec's report of the 27 July 2026 SKC earnings call. CoPoS panel sizes, 2028–2029 volume, and "glass core after 2030" are industry and sell-side (TrendForce, Commercial Times, Ming-Chi Kuo) and are labeled as such; TSMC's transcript does not name CoPoS in the glass answer. SEMCO timing, AMD/AWS as Absolics customers, and "Intel cancelled glass in 2024" are trade-press or rumor, not primary. CTE ranges for silicon (\~2.6–3.2 ppm/K) and organic cores (low-to-mid teens) are standard packaging-literature figures. IBM is cited only as historical TGV-interposer process literature, not as a 2026 product program. CoWoS reticle multiples and 5.5×/14× dates follow TSMC's 2026 symposium and earnings language as used in our CoWoS guide.