> ## Content Index > Fetch the complete content index at: https://www.insidedeeptech.com/llms.txt > Use this file to discover other available public pages before exploring further. # Chiplets and UCIe: A Full Guide to How Modern Chips Are Built From Smaller Dies - URL: https://www.insidedeeptech.com/chiplets-ucie-full-guide/ - Published: 2026-08-17T15:12:35.000Z - Updated: 2026-08-17T15:12:34.000Z - Description: Everything you need to understand why 2026's biggest chips are no longer one piece of silicon: the reticle limit, chiplet economics, proprietary fabrics versus the UCIe standard, and why mix-and-match dies remain more aspiration than product. - Author: Editorial Team - Tags: Semiconductors, AI, Hardware A chiplet is not a smaller chip. It is a die designed from the start to live in a package with other dies, talking over millimeters of interconnect instead of centimeters of board. The product the customer buys — a CPU, a GPU, an AI accelerator — is the package. The silicon inside it is a kit. That kit exists because the alternative ran out of room. A leading-edge lithography scanner can pattern about 26 mm by 33 mm in one exposure, roughly 858 mm². NVIDIA's Hopper H100 was already near that ceiling as a single die. Blackwell and Blackwell Ultra are two reticle-sized dies stitched into one GPU. AMD has been shipping server CPUs as a ring of compute chiplets around an I/O die since 2019\. The [HBM](https://www.insidedeeptech.com/high-bandwidth-memory-hbm-full-guide/) stacks sitting next to every serious AI accelerator are chiplets too, even if nobody markets them that way. What changed in 2026 is not that chiplets arrived. It is that the open interconnect meant to make them interchangeable, Universal Chiplet Interconnect Express (UCIe), now has three generations of specification — 1.0 through 3.0 — while the parts that actually ship still mostly talk over proprietary fabrics. The useful question is which split is real, which standard is load-bearing, and what still has to yield before "mix and match" is a purchase order instead of a keynote. ### Key takeaways - **A chiplet is a functional die in a multi-die package, not a product SKU.** The package is the system-on-chip. Compute, I/O, SRAM, and [HBM](https://www.insidedeeptech.com/high-bandwidth-memory-hbm-full-guide/) can sit on different process nodes and still behave, to software, as one device. - **The reticle, not Moore's Law, is the hard geometric limit.** A 193 nm ArF scanner field is about 26 × 33 mm (\~858 mm²). Anything larger must be stitched, partitioned, or stacked. [EUV lithography](https://www.insidedeeptech.com/euv-lithography-asml-machines-full-guide/) prints the transistors; it does not enlarge the field. - **Yield and mix-and-match economics are why companies do this, not slogans.** Smaller dies defect fewer transistors per unit. Analog, SerDes, and SRAM do not need the newest node. SKUs can be assembled from a library of known-good dies instead of a new mask set for every core count. - **UCIe is the open die-to-die standard. Most 2026 flagship AI parts still use private ones.** The [UCIe Consortium](https://www.uciexpress.org/specifications?ref=insidedeeptech.com) published 1.0 in March 2022, 2.0 in August 2024 (manageability plus UCIe-3D), and 3.0 on 5 August 2025 (48 and 64 GT/s). AMD Infinity Fabric, NVIDIA NV-HBI, and Intel EMIB/AIB still carry the traffic that matters on CPUs and GPUs. - **Advanced packaging is the assembly method. Chiplets are the architecture.** [CoWoS, EMIB, Foveros, and hybrid bonding](https://www.insidedeeptech.com/advanced-packaging-in-chips-explained-a-comprehensive-guide/) are how the dies are joined. UCIe, Infinity Fabric, and NV-HBI are how they speak. Confusing the two produces vendor copy, not a bill of materials. - **A multi-vendor chiplet marketplace is not a 2026 product.** PHY IP, compliance suites, and UCIe-3.0 data rates exist. Shipping SiPs built from two companies' logic dies, bought off a catalog, remain rare. Known-good-die test, thermal design, and security across a vendor boundary are the unsolved industrial problems. ## Chiplets at a glance | Attribute | Detail | | ------------------------ | ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- | | What it is | A die designed to be assembled with other dies into one package that software treats as a single SoC | | What it is not | A smaller monolithic chip, a drop-in PCIe card, or a 2026 open marketplace of mix-and-match logic | | Core trick | Partition the SoC so each function uses an appropriate process node and a die small enough to yield, then reconnect them on-package | | Key hardware | Compute dies, I/O dies, SRAM or cache tiles, HBM stacks, organic substrate or silicon interposer/bridge, die-to-die PHY | | Transmission medium | Millimeters of package traces, silicon bridge, interposer, or hybrid-bonded pads — not centimeters of board SerDes | | Main applications | Server CPUs, AI GPUs and accelerators, client SoCs, networking switches, some automotive and 5G silicon | | Deployed today | AMD EPYC (CCD + IOD); AMD Instinct MI300-class (XCD + IOD + HBM); NVIDIA Blackwell dual-reticle GPUs; Intel tiled Xeon and client SoCs; every HBM-equipped accelerator | | Biggest unsolved problem | Turning a working single-vendor SiP into an interoperable, tested, thermally qualified multi-vendor product | ## What a chiplet actually is Start with the thing it is not. It is not a chip you can socket. It is not a way to skip [EUV](https://www.insidedeeptech.com/euv-lithography-asml-machines-full-guide/) or to ignore the packaging line. And "chiplet architecture" on a slide does not tell you whether the dies share a cache, a memory map, or merely a substrate. Gordon Moore saw the fork in 1965\. In the same paper that named the scaling law, he wrote that it might prove more economical "to build large systems out of smaller functions, which are separately packaged and interconnected." For fifty years the industry took the other fork: put more transistors on one die. That worked until the die itself became the expensive, low-yielding, reticle-limited object. A chiplet is the smaller function. A system-in-package (SiP) is the large system. The die-to-die link is the interconnect Moore was pointing at, moved from the board onto the package so the energy per bit drops by roughly an order of magnitude and the latency drops from tens of nanoseconds toward one or two. Three partitions show up over and over: - **Homogeneous scale-up.** Identical compute dies tiled to beat the reticle. NVIDIA Blackwell's two reticle-sized GPUs, linked by NV-HBI at 10 TB/s, are this. Software sees one CUDA device. - **Heterogeneous disaggregation.** Different functions on different nodes. AMD EPYC puts Zen cores on a leading-edge CCD and memory controllers, PCIe, and Infinity Fabric on a cheaper I/O die. Analog, SerDes, and I/O do not pay 3 nm prices. - **Memory as a chiplet.** [HBM](https://www.insidedeeptech.com/high-bandwidth-memory-hbm-full-guide/) is stacked DRAM with a logic base die, sitting a few millimeters from the GPU on an interposer. It is the highest-volume chiplet in AI, sold by memory companies rather than CPU vendors. [Advanced packaging](https://www.insidedeeptech.com/advanced-packaging-in-chips-explained-a-comprehensive-guide/) is how those partitions become a product: organic 2D substrates, silicon bridges (Intel EMIB), silicon interposers (TSMC CoWoS), and 3D hybrid bonding (TSMC SoIC, Intel Foveros Direct). The architecture question is separate. It is which protocol runs over those wires, who defines the bump map, and whether a die from vendor B can talk to a die from vendor A without a custom PHY. ### The problem the reticle created A scanner field of \~858 mm² is not a suggestion. It is the largest rectangle a 193 nm immersion tool can print in one shot. Interposers can be stitched across multiple fields. Logic dies generally cannot, not if you want one continuous design. Hopper's \~800 mm² class die was already living at that edge. Blackwell's answer, documented in NVIDIA's [Blackwell Ultra architecture note](https://developer.nvidia.com/blog/inside-nvidia-blackwell-ultra-the-chip-powering-the-ai-factory-era/?ref=insidedeeptech.com), is two dies, 208 billion transistors, a shared L2, and a custom die-to-die fabric the company calls NV-HBI. Yield is the other half. Defect density is roughly Poisson. Double the die area and you more than double the chance a killer defect lands on it, which is why a 400 mm² CCD can be a business and an 800 mm² monolithic server CPU often cannot. AMD's EPYC library — many small compute chiplets, one I/O die, bin by core count — is that math made into a product line. [Fifth-generation EPYC](https://www.amd.com/en/newsroom/press-releases/2024-10-10-amd-launches-5th-gen-amd-epyc-cpus-maintaining-le.html?ref=insidedeeptech.com) ("Turin") still uses it: Zen 5 parts up to 128 cores, Zen 5c dense parts up to 192 cores, assembled from up to 16 CCDs (Zen 5) or 12 CCDs (Zen 5c) around a central IOD. The third driver is mixed technology. An HBM PHY, a 112G SerDes, an analog PLL, and a GPU SM array do not want the same process. Chiplets let each of them stay on the node that yields. That is also why [AI chip startups](https://www.insidedeeptech.com/9-ai-chip-startups-challenging-nvidia-in-2026/) chasing NVIDIA so often discover that the hard part is not the datapath. It is getting a CoWoS slot, an HBM allocation, and a die-to-die PHY that actually closes timing, in the same quarter. ## How the dies actually talk A working multi-die package is four problems stacked on top of each other: the physical bumps, the electrical PHY, the link protocol, and the software model that pretends none of this exists. ### Standard package versus advanced package UCIe 1.0 split the physical world in two, and that split is still the one that matters. **Standard package (UCIe-S)** is 2D: traces on an organic substrate, bump pitch 100–130 µm, channel reach up to 25 mm. Each cluster is 16 single-ended lanes. At 32 GT/s that is 64 GB/s per module per direction. The consortium's target power is 0.5 pJ/bit. This is the cost-effective, longer-reach option — the on-package analog of a short board link. **Advanced package (UCIe-A)** is 2.5D: silicon interposer, embedded bridge, or equivalent, bump pitch 25–55 µm, reach up to 2 mm. Each cluster is 64 lanes. At 32 GT/s that is 256 GB/s per module per direction. Target power is 0.25 pJ/bit. Bandwidth density, estimated at a conservative 45 µm pitch, runs to about 1,317 GB/s per mm of shoreline and about 1,350 GB/s/mm². Spare lanes handle defects; standard package degrades width instead. A link is 1, 2, or 4 clusters. Devices must support every rate from 4 GT/s up to their advertised maximum so two dies can train. Sideband is always-on at 800 MHz for training, debug, and management. The consortium's latency target for the PHY plus die-to-die adapter is under 2 ns, bump to bump and back. Those numbers are specification targets from the UCIe 1.0 materials, not measured silicon on a named product. Implementations miss them, beat them, or qualify only a subset. The table is still the right way to read a vendor PHY claim: which package class, which bump pitch, which data rate, which cluster count. ### Protocols: PCIe, CXL, streaming, raw UCIe did not invent a new software model. It reused two that already work at board level. - **PCIe / CXL.io** for discovery, configuration, and I/O attach. Existing drivers see a PCIe device that happens to live on-package. - **CXL.mem and CXL.cache** for memory and coherency attach. A memory chiplet or an accelerator can join the CPU's cache domain without a new ISA. - **Streaming** for whatever on-die fabric the vendor already has — AXI, CHI, a GPU mesh, a switch internal protocol. The UCIe adapter supplies CRC, retry, and link management; it does not rewrite the packets. - **Raw mode** bypasses the adapter. This is how a SerDes, a DSP, or co-packaged optics can sit on the same PHY without a flit engine. That last path is why UCIe 3.0 added mappings for continuous-transmission protocols in raw mode. A SoC-to-DSP chiplet link does not want start-stop flits. The honest limitation: mapping CHI or a proprietary GPU fabric onto UCIe streaming does not make two vendors' caches coherent. It makes the wires interoperable. Coherence, address maps, security, and boot are still product work. ### UCIe-3D and hybrid bonding UCIe 2.0, released in August 2024, added a vertical physical layer. UCIe-3D is aimed at hybrid bonding, with bump pitches from roughly 10–25 µm down to about 1 µm. Bandwidth density scales with the square of pitch, so a move from 25 µm 2.5D to 5 µm 3D is not a tweak. The consortium's 2.0 materials cite order-of-magnitude density gains even at a modest 4 GT/s, because the pad count explodes. 3D is also a thermal and test problem. You cannot probe a hybrid-bonded interface the way you probe a 45 µm microbump. Known-good-die screening has to happen before the bond, or the stack is scrap. That is why 3D cache-on-logic (AMD 3D V-Cache, Intel Foveros) shipped years before 3D logic-on-logic at high volume. ## The UCIe generations, compared | Generation | Date | Ceiling data rate | What it added | What it did not add | | ---------- | ---------- | ---------------------------------- | ---------------------------------------------------------------------------------------------------------------------------------------------------------- | ----------------------------------------------------- | | UCIe 1.0 | Mar 2022 | 32 GT/s | PHY, D2D adapter, PCIe/CXL/streaming, standard vs advanced package, bump maps | Multi-vendor manageability, 3D, automotive extras | | UCIe 1.1 | 2023 | 32 GT/s | Compliance architecture, automotive health monitoring and repair, lower-cost bump maps, simultaneous multiprotocol | A new speed grade | | UCIe 2.0 | Aug 2024 | 32 GT/s (planar) | Optional manageability and UDA (DFx fabric per chiplet), UCIe-3D for hybrid bonding | Faster planar rates | | UCIe 3.0 | 5 Aug 2025 | 48 and 64 GT/s (UCIe-S and UCIe-A) | Doubled planar bandwidth vs 2.0, sideband reach to 100 mm, runtime recalibration, early firmware download, priority sideband, raw-mode continuous mappings | A guarantee that anyone is shipping 64 GT/s in volume | UCIe 3.0 is backward compatible with 2.0, 1.1, and 1.0\. That is the point of a standard: a 32 GT/s 1.0 die should train with a 64 GT/s 3.0 die at 32 GT/s. 3D links in the 2.0/3.0 materials stay at SoC-like frequencies (the public briefings put them at or below 4 GT/s) because the density comes from pad count, not from clocking a hybrid bond like a SerDes. Founding members in March 2022 were ASE, AMD, Arm, Google Cloud, Intel, Meta, Microsoft, Qualcomm, Samsung, and TSMC. NVIDIA and Alibaba joined the board at incorporation in August 2022\. The consortium now cites 150-plus members. Membership is not the same as a shipping interoperable SiP. ## What actually shipped The products that matter in 2026 were designed before UCIe 3.0 existed. They tell you what chiplets do when a single company owns every die. ### AMD: the production chiplet company EPYC is the existence proof. Since Zen 2, server CPUs have been compute chiplets plus a central I/O die, linked by Infinity Fabric over organic substrate. Turin did not change the idea. It changed the cores (Zen 5 / Zen 5c), the CCD count, and the I/O: 12 channels of DDR5, up to 128 lanes of PCIe Gen 5, CXL 2.0\. Each CCD talks to the IOD over a dedicated GMI link. Cores on different CCDs pay a fabric hop to share data or to reach memory. That hop is the cost of the yield win. MI300X is the aggressive version. AMD's datasheet and the IEEE Micro interconnect paper describe eight CDNA 3 accelerator complex dies stacked with TSMC SoIC hybrid bonding onto four I/O dies, sitting on a CoWoS interposer with eight HBM3 stacks: 304 compute units, 192 GB, 5.3 TB/s. Four IODs, not one. Compute on top of I/O on top of an interposer. The same XCD library is reused in MI300A with Zen 4 CPU chiplets. That reuse is the chiplet pitch working as advertised — inside one vendor's roadmap. ### NVIDIA: two reticles, one GPU Blackwell and Blackwell Ultra are not a sea of small chiplets. They are two reticle-limit dies made to look like one GPU. NV-HBI provides 10 TB/s between them, with a shared coherent L2\. The package still carries eight HBM stacks (192 GB on Blackwell, 288 GB on Ultra in the full SKU) and NVLink-C2C at 900 GB/s to a Grace CPU. The architectural claim NVIDIA cares about is that CUDA does not change. The manufacturing claim is that 208 billion transistors would not yield as one die. NV-HBI is not UCIe. Neither is NVLink-C2C. NVIDIA sits on the UCIe board. The GPU that generates the company's data-center revenue uses a private die-to-die. ### Intel: bridges and tiles Intel's commercial chiplet story is EMIB (a small silicon bridge in the organic substrate, used where the dies meet) plus Foveros (active 3D stacking). Ponte Vecchio was the maximalist version — dozens of tiles, EMIB plus Foveros, a yield and schedule object lesson. Client SoCs (Meteor Lake and successors) and Xeon 6 tiles are the volume version: compute tiles, I/O tiles, graphics tiles, connected by EMIB rather than a giant interposer. Intel's Advanced Interface Bus (AIB) was a major input to the UCIe PHY. That does not mean current Xeon tiles speak UCIe to a third-party die. ### Everyone else, including HBM Apple UltraFusion, Amazon Trainium/Inferentia 2.5D, Google TPU interposers, and every CoWoS-attached accelerator are chiplet systems in the packaging sense. The HBM cube is the one chiplet that *is* multi-vendor in practice: SK hynix, Samsung, and Micron sell stacks that sit next to logic they did not design. The interface is a JEDEC HBM spec, not UCIe. That is the closest thing the industry has to a working chiplet marketplace, and it is a memory marketplace. ## Proprietary fabric versus open standard This is the distinction most explainers flatten. | Interconnect | Owner | Where it runs | Open? | 2026 role | | ------------------------- | --------------- | -------------------------------------------------- | --------------------------------------- | -------------------------------------------------------------------- | | Infinity Fabric / GMI | AMD | EPYC CCD↔IOD, MI300 XCD/IOD, GPU-GPU scale-up | No | Production CPUs and Instinct | | NV-HBI | NVIDIA | Blackwell die↔die | No | Dual-reticle GPUs | | NVLink-C2C | NVIDIA | Grace↔GPU, some CPU-GPU coherency | No | Superchips | | EMIB + AIB / tile fabrics | Intel | Xeon tiles, client SoCs, some GPUs | AIB influenced UCIe; products are Intel | Production tiled CPUs | | HBM PHY | JEDEC + vendors | GPU/ASIC ↔ HBM stack | Standard (JEDEC), not UCIe | Every HBM accelerator | | UCIe | Consortium | PHY IP, test chips, some networking/client designs | Yes | Spec-complete through 3.0; still the minority of flagship AI traffic | UCIe's pitch is that the package should work like the board: a slot, a standard PHY, plug-and-play IP. PCIe did that for cards. CXL is trying to do it for memory. UCIe is trying to do it for dies. The reason flagship GPUs have not switched is straightforward. A 10 TB/s coherent fabric between two halves of one GPU is a custom analog and a custom cache protocol. Standardizing it would freeze a competitive interface. UCIe is more valuable where the dies really do come from different teams: an I/O chiplet from a foundry IP catalog, a DSP, co-packaged optics, a CXL memory tile, an automotive companion die. Those sockets are real. They are not the 2026 AI GPU. ## What is real and what is hype ### Real - Chiplets are how every high-end CPU and almost every HBM-equipped accelerator is built in 2026\. This is not a research topic. - The reticle limit and Poisson yield are the physical reasons, not a marketing story. - UCIe 1.0 through 3.0 is a complete, publicly requestable specification with bump maps, protocols, and a compliance path. 3.0's 64 GT/s doubles the 2.0 planar ceiling. - HBM is a working, multi-vendor on-package chiplet ecosystem — under a different standard. - Die-to-die energy is the point. UCIe's 0.25–0.5 pJ/bit targets are about 20× below a \~10 pJ/bit board SerDes. Short reach is the whole product. ### Hype - **"You can mix and match chiplets from any vendor."** You can mix and match *if* both sides implemented the same UCIe package class, trained at a common rate, agreed a protocol, passed compliance, and solved boot, security, thermal, and known-good-die. Almost no commercial AI or CPU SiP does that across two logic vendors in 2026. - **"UCIe replaces CoWoS / EMIB / Foveros."** Those are packaging technologies. UCIe is an interconnect spec that runs on top of them. You still need the assembly line. - **"Chiplets beat the memory wall."** They move compute next to HBM. They do not add capacity or bandwidth beyond what the stacks and the interposer provide. Bandwidth-starved inference is still a memory problem, which is why [inference TCO](https://www.insidedeeptech.com/the-real-cost-of-running-ai-in-2026-inference-chips-compared/) keeps coming back to SRAM-heavy designs and to HBM allocation. - **"64 GT/s UCIe 3.0 is in your 2026 GPU."** The spec is dated August 2025\. Design-in, PHY hardening, and package qualification lag a spec by years. Treat 3.0 as the next PHY generation, not as a SKU. ## A realistic timeline | Horizon | What is actually available | Confidence | | ----------------------- | ----------------------------------------------------------------------------------------------------------------------------------------------- | --------------------------------------------------------------------------- | | Now (2026) | Single-vendor chiplet CPUs and GPUs at scale; HBM as a multi-vendor memory chiplet; UCIe 1.x/2.0 PHY IP and test chips; UCIe 3.0 spec published | Deployed (products) / spec-complete (UCIe 3.0) | | Near term (2027–2028) | More UCIe-attached I/O, optics, and CXL memory tiles; first commercially interesting multi-vendor logic+I/O SiPs; 48/64 GT/s PHYs in design-in | High that IP ships; medium that two logic vendors share a package in volume | | Medium term (2028–2031) | UCIe-3D in selected cache-on-logic and logic-on-logic stacks; a thin catalog of compliant chiplets for networking and automotive | Plausible, test- and thermal-limited | | Long term (2030s) | A PCIe-like marketplace for dies, with security and manageability that span vendors | Speculative on schedule; directionally what the consortium is for | One useful heuristic: ask which protocol the dies speak, which package class, and whether a second vendor's die has ever trained on that PHY in a qualified product. Do not ask whether the part "uses chiplets." Everything serious does. ## The bottom line 2026 is the year chiplets stopped being an AMD talking point and became the default way to build anything that no longer fits on one reticle. The physics is old. Smaller dies yield. Mixed nodes are cheaper. On-package wires beat board SerDes by an order of magnitude in energy. The new work is industrial: a bump map two companies can share, a known-good-die flow that does not scrap a $3,000 package, a thermal design for 3D, and a manageability fabric that can reset one chiplet without bricking the rest. UCIe is the attempt to make that industrial layer look like PCIe. Versions 1.0 through 3.0 are real specifications. 64 GT/s is a real number in a real document dated August 2025\. The GPUs and CPUs that dominate [AI infrastructure](https://www.insidedeeptech.com/the-state-of-ai-infrastructure-2026-compute-power-and-constraints/) still speak Infinity Fabric, NV-HBI, and EMIB. Both facts can be true at once. For anyone making decisions today, the split is clean. If the question is how a 2026 CPU or GPU is built, you are looking at chiplets, a 2.5D or 3D package, and a proprietary die-to-die. If the question is whether a vendor's "open chiplet" story is real, ask for the UCIe package class, the trained data rate, the protocol (CXL, streaming, or raw), and the name of the other company's die in the same package. Packaging capacity and HBM still decide how many of those packages the industry can ship. ## Frequently asked questions ### What is a chiplet? A chiplet is a silicon die designed to be assembled with other dies into a single package. The package is the product. Compute, I/O, cache, and memory can occupy different dies, often on different process nodes, and still appear to software as one SoC. ### How is a chiplet different from advanced packaging? Chiplets are the architectural split — which functions live on which die. Advanced packaging is the assembly technology that joins them: organic substrates, silicon interposers, embedded bridges, hybrid bonding. You can package two chiplets with CoWoS or with EMIB. You cannot "use CoWoS instead of chiplets." ### What is UCIe? Universal Chiplet Interconnect Express is an open industry standard for die-to-die links inside a package. It specifies the physical layer (bump maps, data rates, standard vs advanced vs 3D package), a die-to-die adapter (CRC, retry, link training), and protocols (PCIe, CXL, streaming, raw). The UCIe Consortium published 1.0 in March 2022, 2.0 in August 2024, and 3.0 in August 2025. ### What data rates does UCIe support? UCIe 1.0 and 2.0 planar links run 4, 8, 12, 16, 24, and 32 GT/s. UCIe 3.0 adds 48 and 64 GT/s for standard and advanced packages, doubling the 2.0 ceiling. 3D links in the 2.0 generation are specified around SoC frequencies (public briefings: ≤4 GT/s), with density coming from much finer pad pitch. ### Do NVIDIA and AMD GPUs use UCIe? Not for the links that define those products. NVIDIA Blackwell uses NV-HBI between its two compute dies. AMD EPYC and Instinct use Infinity Fabric / GMI. Both companies are UCIe Consortium members. Membership is not the same as a shipping UCIe GPU fabric. ### Why not just make a bigger chip? The scanner field tops out near 858 mm², and a die that large yields badly. Splitting into chiplets also lets I/O and analog stay on cheaper nodes and lets a vendor assemble many SKUs from one compute-die library. NVIDIA's two-reticle Blackwell is what "just make it bigger" looks like after you hit the field size. ### Are HBM stacks chiplets? Functionally yes: they are separately manufactured dies (a DRAM stack plus a logic base die) attached on-package to a GPU or ASIC over a JEDEC interface. They are not UCIe chiplets. They are the one on-package component that already has a multi-vendor market. ### When will I be able to buy mix-and-match chiplets? Not as a catalog in 2026\. PHY IP and compliance work are ahead of product. The realistic near-term mix is a vendor's SoC plus a third-party I/O, optics, or CXL memory tile that both sides designed to UCIe. Two companies' CPU or GPU compute dies in one package, bought independently, is a later, harder problem — test, thermal, security, and business model, not just a spec. ## Methodology This guide is based on primary consortium, vendor, and standards disclosures available as of 17 August 2026: the UCIe Consortium specification pages for 1.0, 1.1, 2.0, and 3.0 (3.0 announced 5 August 2025: 48/64 GT/s, 100 mm sideband, backward compatibility); Debendra Das Sharma's UCIe white-paper presentation of 1.0 physical-layer KPIs (standard vs advanced package, 16/64-lane clusters, 0.5/0.25 pJ/bit targets, <2 ns PHY+adapter latency, shoreline and area densities at 110 µm / 45 µm); the UCIe 2.0 manageability and UCIe-3D materials (hybrid-bond pitches from \~10–25 µm to \~1 µm); NVIDIA's Blackwell Ultra technical blog (dual-reticle design, 208 billion transistors, 10 TB/s NV-HBI, 288 GB HBM3E on the full Ultra SKU); AMD's 10 October 2024 EPYC 9005 launch (Zen 5 up to 128 cores, Zen 5c up to 192 cores) and the AMD Instinct MI300X datasheet (8 XCDs, 4 IODs, 8 HBM3 stacks, 192 GB, 5.3 TB/s); and AMD's EPYC 9005 architecture overview (CCD-to-IOD GMI, 12-channel DDR5, up to 16 CCDs on Zen 5). Reticle-limit geometry (≈26 × 33 mm, \~858 mm²) is the standard 193 nm ArF scanner field used across foundry and packaging literature; it is not a TSMC-unique number. UCIe pJ/bit and GB/s/mm figures are consortium targets, not independent measurements of a named commercial PHY. "150+ members" is the consortium's own count as of the 3.0 announcement and is not a shipping-product census.