> ## Content Index > Fetch the complete content index at: https://www.insidedeeptech.com/llms.txt > Use this file to discover other available public pages before exploring further. # CFET: A Full Guide to Stacked Nanosheet Transistors After GAAFET - URL: https://www.insidedeeptech.com/cfet-complementary-fet-full-guide/ - Published: 2026-09-10T06:48:26.000Z - Updated: 2026-09-10T08:17:33.000Z - Description: CFET stacks nFET and pFET into one footprint after GAAFET: Samsung's 42 nm gate-pitch 2026 VLSI Best Paper, imec's A7 / ~2033 commercial call, mCFET vs sCFET, and why volume chips still wait. - Author: Inside Deep Tech Editorial - Tags: Semiconductors, Hardware, AI GAAFET bought leading-edge logic another density chapter by wrapping the gate around stacked nanosheets. It did not invent a second floorplan for CMOS pairs. nFET and pFET still sit side by side. A **complementary FET** (**CFET**) stacks those polarities into one footprint: one device above the other, separated by **middle dielectric isolation** (**MDI**). Samsung's Semiconductor Research Center won Best Paper recognition at the 2026 VLSI Symposium for a 3D Stacked FET at **42 nm gate pitch** with triple-stacked nanosheet channels in both n and p devices. Imec's May 2026 roadmap call, as reported by IEEE Spectrum, puts commercial CFET introduction around **2033 at the A7 node**. This guide covers how CFET differs from [GAAFET nanosheet transistors](https://www.insidedeeptech.com/gaafet-nanosheet-transistors-full-guide/), why **contacted poly pitch** (**CPP**) and **track height** (5.5T today, 4.5T and 3T with CFET) matter, how **monolithic CFET** (**mCFET**) differs from **sequential CFET** (**sCFET**), what Intel, Samsung, TSMC, and imec have actually demoed as of September 2026, and where the honest limits sit. Backside power is covered in the [PowerVia / backside power guide](https://www.insidedeeptech.com/backside-power-delivery-powervia-full-guide/). Patterning ceilings live in the [High-NA EUV guide](https://www.insidedeeptech.com/high-na-euv-lithography-full-guide/). Die stacking density is [hybrid bonding / SoIC / Foveros Direct](https://www.insidedeeptech.com/hybrid-bonding-soic-foveros-direct-full-guide/). Do not treat CFET as a substitute for packaging, HBM, or CoWoS. ## Key Takeaways ✅ Exactly five takeaways for operators and investors sizing the post-GAAFET transistor roadmap as of September 2026. - CFET stacks nFET and pFET vertically in one footprint after GAAFET leaves CMOS pairs side by side (IEEE Spectrum / imec roadmap, May 2026). - Samsung's 2026 VLSI Best Paper showed a 42 nm gate-pitch 3D Stacked FET with triple nanosheets in both polarities and MDI isolation (Samsung Semiconductor tech blog). - Imec expects commercial CFET around 2033 at A7, with cells moving from \~5.5T GAA toward 4.5T and 3T (IEEE Spectrum; imec Part 1, Sep 2026). - mCFET is a single process sequence; sCFET patterns top and bottom independently with two wafer flips and harder alignment (imec Part 1). - Prototypes are not volume chips: process versions remain open, interconnect congestion eats density, and High-NA/EUV still gate patterning. ## CFET at a glance | Attribute | Detail | | ------------------------ | ------------------------------------------------------------------------------------------------------------------------------------------- | | What it is | Complementary FET: nFET and pFET stacked vertically in one footprint, usually as nanosheet channels with MDI between polarities | | What it is not | A shipping foundry node in 2026; a FinFET; a packaging substitute for HBM/CoWoS; a free lunch on interconnect congestion | | Core trick | Recover lateral area by stacking CMOS pairs instead of placing them side by side, enabling shorter standard cells (4.5T → 3T class) | | Key modules | Si/SiGe multilayer epitaxy; MDI; backside contacts / BDI; multi-Vt gate stacks (dipole-middle); High-NA or Low-NA EUV for CPP | | Status (Sep 2026) | Intel, Samsung, and TSMC have prototype CFETs; Samsung VLSI 2026 Best Paper at 42 nm gate pitch; imec modules advancing mCFET/sCFET | | Roadmap call | Imec: commercial introduction around 2033 at A7; later evolution, then \~2041 interest in 2D channels mainly for power | | Biggest unsolved problem | Settling which process version wins (mCFET vs sCFET and isolation schemes), contacting the bottom device, and BEOL routability at 3T height | ## Why CFET comes after GAAFET Let's start with what GAAFET already fixed. FinFET electrostatics ran out of headroom as fins got thinner. Nanosheet GAA wraps the gate around multiple suspended channels and restores control. Imec's Part 1 article (published about 7 September 2026) states GAA nanosheet scales to about the **A10** generation with **5.5-track** (5.5T) standard cells. Here's the problem. Track height is the cell's vertical budget in metal tracks. Shrinking CPP (the contacted poly pitch, the spacing from one transistor gate to the next) helps, but nFET and pFET still consume lateral floorplan when they sit beside each other. At some point the cell can't get shorter without stacking the pair. That means CFET is the architecture that unlocks **4.5T** cells and, on imec's roadmap language, down to **3T**, extending classical CMOS scaling toward **A3**. Imec also frames A7 as the node where CFET becomes the likely device transition, matching Spectrum's May 2026 reporting of commercial introduction around 2033. On the flip side, CFET doesn't retire EUV. Gate patterning, tip-to-tip, and cut masks still sit on Low-NA or [High-NA EUV](https://www.insidedeeptech.com/high-na-euv-lithography-full-guide/) tools. Stacking transistors is orthogonal to printing finer lines. ## How a CFET is built At first glance, the idea is simple: put PMOS on NMOS (or the reverse) and share a footprint. The process is not. The likely **monolithic** path, as Spectrum summarizes from imec, deposits alternating **Si/SiGe** layers, patterns trenches, then selectively etches SiGe to leave suspended silicon nanosheets. The top set becomes one polarity. The bottom set becomes the other. **MDI** sits between them so each device can take a different gate stack. Samsung's VLSI write-up stresses that MDI is not cosmetic insulation: n and p need different gate materials, and a too-thin or mis-placed MDI couples the floors of the "apartment." Imec splits integration into two complementary tracks. | Path | How it works | Strength | Hard part | | ------------------ | ------------------------------------------------------------------------------------------------------- | ----------------------------------------------------------------------------- | ------------------------------------------------------------------------- | | mCFET (monolithic) | Single process sequence; common gate stack options; high-aspect-ratio modules around one tall structure | Believed fastest industrial path pending alignment progress (imec Part 1) | Patterning, deposition, and selective removal inside a tall, narrow stack | | sCFET (sequential) | Top and bottom patterned independently with dedicated masks; two wafer flips | Simpler individual steps; better isolation and crystal-plane matching options | Duplicated steps; wafer distortion; front-to-back alignment | Spectrum notes a bonded/sequential option that grows the top device layers on a second wafer, then bonds them so isolation and crystal orientation can favor PMOS and NMOS separately. Intel has been testing that scheme. Imec still calls mCFET the faster industrial path if alignment for sCFET doesn't catch up. ## Who has demoed what As of September 2026, the big three all have prototype CFETs. That is not the same as a volume process of record. | Org | Published milestone | Pitch / structure notes | Source class | | ------- | --------------------------------------------------------------------------------------------------- | --------------------------------------------------------------------------------------------------------------------------- | ----------------------------------------- | | Samsung | 2026 VLSI Best Paper (June 14-18 symposium); review score 8.29/10; Technical Highlights / Press Kit | 42 nm gate pitch; triple nanosheets in both n and p; MDI; electrical control + wafer uniformity shown | Samsung Semiconductor tech blog | | TSMC | IEDM (December prior to Spectrum's May 2026 piece) | Compact memory cell + ring oscillator; earlier 48 nm-class CPP demos in historical coverage | IEEE Spectrum May 2026; Spectrum Dec 2023 | | Intel | Historical CFET inverter; sequential/bonded isolation work for VLSI reporting window | Earlier: single-fin inverter, backside contact, CPP 60 nm class, 3 nanosheets/device, separation 50→30 nm | IEEE Spectrum Dec 2023; May 2026 | | imec | 2026 VLSI modules + Sep 2026 Part 1 article | Backside contact: bottom pFET drive 5×; access R 1753→378 Ω·µm; survival yield 45%→85%; dipole-middle \~30 mV nFET Vt shift | imec Part 1 | Samsung brands the device **3D Stacked FET** and maps the industry label to CFET. The evolution line in its blog is explicit: Planar → FinFET → GAA → 3D Stacked FET. The 42 nm gate pitch is the density headline versus earlier 48 nm-class public demos discussed in secondary coverage. First of all, read demos as module readiness, not as a foundry quote. Samsung demonstrated current control and across-wafer uniformity. It did not claim volume production. [GAAFET and Nanosheet Transistors: A Full Guide to How Chips Leave FinFET BehindThe nanosheet chapter CFET extends: why FinFET ran out of room, how GAA wraps the channel, and what shipping nodes actually mean.![](https://www.insidedeeptech.com/favicon.ico)Inside Deep Tech](https://www.insidedeeptech.com/gaafet-nanosheet-transistors-full-guide/) ## Contacts, MDI, backside power, and multi-Vt Of course, stacking the channels is only half the bill of materials. You still have to contact the bottom device, isolate the floors, deliver power, and set multiple threshold voltages without eating the nanosheet gap. **Backside contacting** of the bottom source/drain improves contact resistance and opens process window for the top device. Imec's 2026 VLSI module pairs a **frontside BDI** with a **backside BDI** so the bottom SiGe:B epi isn't seeded by the substrate in a way that wastes contact metal volume. Reported results: bottom pFET drive current **5×** versus the conventional backside scheme, access resistance from **1753 to 378 Ω·µm**, and survival yield from **45% to 85%**. That module sits next to the broader industry move of putting power rails under the transistor layer. If you're sizing racks and dies, read the [backside power delivery guide](https://www.insidedeeptech.com/backside-power-delivery-powervia-full-guide/) in parallel. CFET makes backside contacts more valuable. It does not invent PowerVia. For multi-Vt, space between nanosheets is too tight for thick work-function metal stacks. Imec's **dipole-middle** gate stack locks a La-based shifter in a thin HfO2 sandwich at lower thermal budget, aiming compatibility with low-temperature CFET replacement metal gate flows. The 2026 VLSI demo showed about a **30 mV** nFET Vt reduction versus a reference where the shifter was removed before lock-in. Here's why that matters for buyers: a CFET node that can't offer multiple Vt flavors is a science project. Logic libraries need HVt/LVt/SVt corners even when the devices are stacked. ## Honest limits Prototypes are not production. Imec's commercial intro call is around 2033\. That is seven years of module engineering after the 2026 demos, not a 2027 SKU. - **Process version still open.** Paul Heremans told Spectrum that many CFET versions remain open. mCFET vs sCFET, isolation schemes, and contact flows are competing pathfinding tracks, not a frozen POR. - **Interconnect congestion eats density.** Shorter cells pack more gates, then the BEOL has to route them. Imec's Part 2 agenda explicitly studies BEOL routability for CFET standard cells. Area wins on the device can shrink at the block level. - **Not a packaging substitute.** CFET densifies CMOS pairs on a logic die. It does not replace HBM stacks, CoWoS interposers, or hybrid-bonded chiplets. Those remain separate bottlenecks. - **Lithography still gates patterning.** CPP and tip-to-tip still need EUV, including High-NA where foundries choose it. Stacking doesn't print a smaller pitch by itself. - **Yield and thermal history.** Tall stacks, wafer flips, and low-temperature RMG constraints make survival yield a first-class metric. Imec publishing 45%→85% on bottom pFET survival is the tell: yield is still the story. ⚠️ Named downside: CFET is a bad fit for near-term BOM planning if your product needs a shipping foundry node before the early 2030s, if your density problem is packaging or memory bandwidth rather than standard-cell height, or if your team is still finishing GAAFET yield on A14/A10-class flows. [Read the GAAFET nanosheet guide](https://www.insidedeeptech.com/gaafet-nanosheet-transistors-full-guide/) ## Inside Deep Tech's take 💡 Inside Deep Tech's take: treat CFET as the credible post-GAAFET device architecture on imec's A7/\~2033 calendar, not as a 2026 purchasing decision. Samsung's 42 nm VLSI Best Paper proves the stack can shrink. Imec's backside-contact and dipole-middle modules prove the supporting process kit is moving. Until a foundry freezes mCFET vs sCFET and quotes a process of record, budget GAAFET yield and High-NA capacity first. ## What happens next Through late 2026 and 2027, watch three signals. First, whether mCFET stays the industrial favorite or sCFET alignment numbers close the gap. Second, whether backside contact and MDI modules keep posting yield and resistance wins at tighter CPP. Third, whether DTCO papers show 3T cells that remain routable without exploding metal pitch. Further out, Spectrum's May 2026 imec roadmap piece puts a later CFET evolution phase, then roughly **2041** interest in swapping silicon channels for **2D semiconductors** such as MoS2, mainly for power. In parallel, imec's **CMOS 2.0** story stacks heterogeneous functional tiers with dense 3D interconnects. Wafer-to-wafer bonding pitches in development around **200 nm** imply on the order of **25 million interconnects per mm²**. That packaging density is why [hybrid bonding](https://www.insidedeeptech.com/hybrid-bonding-soic-foveros-direct-full-guide/) stays on the same reading list as CFET. Operators and investors should keep CFET on the transistor roadmap column, GAAFET on the shipping column, and packaging on its own column. Mixing those columns is how decks invent phantom density. --- [Explore Inside Deep Tech coverage](https://www.insidedeeptech.com/) ## FAQ #### What is a CFET? A complementary FET stacks nFET and pFET vertically in one footprint instead of placing them side by side. Industry also uses Samsung's "3D Stacked FET" label for the same architectural idea built on nanosheet GAA channels with middle dielectric isolation. #### How is CFET different from GAAFET? GAAFET wraps the gate around nanosheet channels but still lays CMOS pairs laterally. CFET keeps the nanosheet idea and stacks the polarities. That stack is what unlocks shorter standard cells (4.5T and toward 3T on imec's roadmap) after GAA reaches roughly A10 at 5.5T. #### What are mCFET and sCFET? mCFET builds the vertical device in one process sequence. sCFET patterns top and bottom devices independently and uses two wafer flips. Imec currently views mCFET as the faster industrial path pending better alignment for sequential flows. #### When will CFET reach commercial chips? Imec predicts commercial introduction around 2033 at the A7 node, per IEEE Spectrum's May 19, 2026 roadmap coverage. 2026 VLSI results are prototypes and modules, not a foundry process of record you can buy in volume today. #### What did Samsung show at 2026 VLSI? Samsung presented a 3D Stacked FET at 42 nm gate pitch with triple-stacked nanosheet channels in both n and p devices, plus MDI isolation. The paper earned Best Paper recognition with an 8.29/10 review score and appeared in the VLSI Technical Highlights / Press Kit. #### Why do backside contacts and MDI matter? MDI electrically separates the upper and lower transistors so each can use a different gate stack. Backside contacts reach the bottom source/drain without choking the top device. Imec's 2026 module cut bottom pFET access resistance from 1753 to 378 Ω·µm and raised survival yield from 45% to 85% versus its conventional backside scheme. #### Should my 2026-2028 product plan assume CFET? No. Plan shipping products on GAAFET nodes and packaging roadmaps you can actually buy. Keep CFET in the mid-2030s transistor column, and treat 2026 demos as evidence the architecture is real, not as a BOM line item. --- Primary sources for this guide include Samuel K. Moore's May 19, 2026 IEEE Spectrum report on imec's semiconductor technology roadmap ([spectrum.ieee.org/semiconductor-technology-roadmap](https://spectrum.ieee.org/semiconductor-technology-roadmap?ref=insidedeeptech.com)), Samsung Semiconductor's 2026 VLSI Best Paper tech blog on 3D Stacked FET at 42 nm gate pitch ([semiconductor.samsung.com tech blog](https://semiconductor.samsung.com/news-events/tech-blog/from-gaa-to-3d-stacked-fet-expanding-the-transistor-into-the-third-dimension/?ref=insidedeeptech.com)), and imec's September 2026 Part 1 article on CFET integration modules and standard-cell scaling ([imec-int.com CFET Part 1](https://www.imec-int.com/en/articles/advancing-cfet-based-device-roadmap-novel-integration-modules-and-standard-cell?ref=insidedeeptech.com)). Historical demo pitches cite Spectrum's December 16, 2023 CFET overview. Figures are dated as of September 2026 editorial review.